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user?s manual v850es 32-bit microprocessor core architecture document no. u15943ej3v0um00 (3rd edition) date published april 2004 n cp(k) printed in japan 2002
user?s manual u15943ej3v0um 2 [memo]
user?s manual u15943ej3v0um 3 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. notes for cmos devices
user?s manual u15943ej3v0um 4 these commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. diversion contrary to the law of that country is prohibited. ? ? ? ? ? ?
user?s manual u15943ej3v0um 5 regional information ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [global support] http://www.necel.com/en/support/support.html nec electronics america, inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 nec electronics hong kong ltd. hong kong tel: 2886-9318 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-558-3737 nec electronics shanghai ltd. shanghai, p.r. china tel: 021-5888-5400 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 nec electronics singapore pte. ltd. novena square, singapore tel: 6253-8311 j04.1 n ec electronics (europe) gmbh duesseldorf, germany tel: 0211-65030 ? sucursal en espa?a madrid, spain tel: 091-504 27 87 vlizy-villacoublay, france tel: 01-30-67 58 00 ? succursale fran?aise ? filiale italiana milano, italy tel: 02-66 75 41 ? branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 ? tyskland filial taeby, sweden tel: 08-63 80 820 ? united kingdom branch milton keynes, uk tel: 01908-691-133 some information contained in this document may vary from country to country. before using any nec electronics product in your application, piease contact the nec electronics office in your country to obtain a list of authorized representatives and distributors. they will verify:
6 user?s manual u15943ej3v0um preface target readers ? ? ? ? ?
7 user?s manual u15943ej3v0um conventions data significance: higher digits on the left and lower digits on the right active low representation: b (b is appended to pin or signal name) note : footnote for item marked with note in the text caution : information requiring particular attention remark : supplementary information numerical representation: binary ... or b decimal ... hexadecimal ... h prefix indicating the power of 2 (address space, memory capacity): k (kilo): 2 10 = 1,024 m (mega): 2 20 = 1,024 2 g (giga): 2 30 = 1,024 3
8 user?s manual u15943ej3v0um contents chapter 1 general........................................................................................................... ................ 12 1.1 features ................................................................................................................... ...................... 13 1.2 internal configuration ..................................................................................................... ............. 14 chapter 2 register set..................................................................................................... ............ 15 2.1 program registers.......................................................................................................... .............. 16 2.2 system registers........................................................................................................... ............... 18 2.2.1 interrupt status savi ng registers (e ipc, eipsw).......................................................................... .... 19 2.2.2 nmi status saving registers (f epc, fepsw) ................................................................................ .. 20 2.2.3 exception caus e register (ecr) ........................................................................................... ............ 20 2.2.4 program stat us word (psw) ................................................................................................ ............ 21 2.2.5 callt caller status savi ng registers (ctp c, ctpsw ).................................................................... 22 2.2.6 exception/debug trap status saving regist ers (dbpc, dbpsw) ...................................................... 23 2.2.7 callt base pointer (ctbp) ................................................................................................ ............ 23 2.2.8 debug interface register (dir) ........................................................................................... .............. 24 chapter 3 data type........................................................................................................ ............... 25 3.1 data format ................................................................................................................ ................... 25 3.2 data representa tion........................................................................................................ ............. 27 3.2.1 in teger .................................................................................................................. ............................ 27 3.2.2 unsi gned int eger ......................................................................................................... ..................... 27 3.2.3 bit...................................................................................................................... ............................... 27 3.3 data alignment............................................................................................................. ................. 27 chapter 4 address space .................................................................................................... ........ 28 4.1 memory map ................................................................................................................. ................. 29 4.2 addressing mode............................................................................................................ .............. 30 4.2.1 instruct ion addr ess...................................................................................................... ..................... 30 4.2.2 oper and addres s .......................................................................................................... ................... 32 chapter 5 instruction....................................................................................................... ............. 34 5.1 instruction format ......................................................................................................... ............... 34 5.2 outline of instructi ons .................................................................................................... ............. 38 5.3 instruction set............................................................................................................ ................... 42 add ............................................................................................................................ ................................... 44 addi ........................................................................................................................... ................................... 45 and ............................................................................................................................ ................................... 46 andi ........................................................................................................................... ................................... 47 bcond.......................................................................................................................... ................................... 48 bsh ............................................................................................................................ ................................... 50 bsw............................................................................................................................ ................................... 51 callt .......................................................................................................................... .................................. 52 clr1........................................................................................................................... ................................... 53
9 user?s manual u15943ej3v0um cmov........................................................................................................................... ..................................54 cmp............................................................................................................................ ....................................55 ctret.......................................................................................................................... ..................................56 dbret .......................................................................................................................... .................................57 dbtrap ......................................................................................................................... ................................58 di ............................................................................................................................. .......................................59 dispose........................................................................................................................ ................................60 div............................................................................................................................ ......................................62 divh ........................................................................................................................... ....................................63 divhu .......................................................................................................................... ..................................65 divu ........................................................................................................................... ....................................66 ei ............................................................................................................................. .......................................67 halt ........................................................................................................................... ...................................68 hsw ............................................................................................................................ ...................................69 jarl........................................................................................................................... ....................................70 jmp ............................................................................................................................ ....................................71 jr ............................................................................................................................. ......................................72 ld.b........................................................................................................................... .....................................73 ld.bu .......................................................................................................................... ...................................74 ld.h ........................................................................................................................... ....................................75 ld.hu.......................................................................................................................... ...................................76 ld.w........................................................................................................................... ....................................77 ldsr ........................................................................................................................... ...................................78 mov ............................................................................................................................ ...................................79 movea.......................................................................................................................... .................................80 movhi.......................................................................................................................... ..................................81 mul ............................................................................................................................ ....................................82 mulh ........................................................................................................................... ..................................83 mulhi .......................................................................................................................... ..................................84 mulu ........................................................................................................................... ..................................85 nop............................................................................................................................ ....................................86 not ............................................................................................................................ ....................................87 not1 ........................................................................................................................... ...................................88 or ............................................................................................................................. .....................................89 ori ............................................................................................................................ .....................................90 prepare ........................................................................................................................ ..............................91 reti ........................................................................................................................... ....................................93 sar ............................................................................................................................ ....................................95 sasf ........................................................................................................................... ...................................96 satadd ......................................................................................................................... ................................97 satsub ......................................................................................................................... ................................98 satsubi ........................................................................................................................ ................................99 satsubr........................................................................................................................ .............................100 set1........................................................................................................................... ..................................101 setf ........................................................................................................................... .................................102 shl............................................................................................................................ ...................................104 shr ............................................................................................................................ ..................................105 sld.b .......................................................................................................................... .................................106
10 user?s manual u15943ej3v0um sld.bu......................................................................................................................... ............................... 107 sld.h .......................................................................................................................... ................................ 108 sld.hu......................................................................................................................... ............................... 109 sld.w .......................................................................................................................... ............................... 110 sst.b .......................................................................................................................... ................................ 111 sst.h .......................................................................................................................... ................................ 112 sst.w .......................................................................................................................... ............................... 113 st.b........................................................................................................................... .................................. 114 st.h........................................................................................................................... .................................. 115 st.w........................................................................................................................... ................................. 116 stsr ........................................................................................................................... ................................ 117 sub ............................................................................................................................ ................................. 118 subr........................................................................................................................... ................................ 119 switch......................................................................................................................... .............................. 120 sxb............................................................................................................................ .................................. 121 sxh ............................................................................................................................ ................................. 122 trap ........................................................................................................................... ................................ 123 tst ............................................................................................................................ .................................. 124 tst1 ........................................................................................................................... ................................. 125 xor ............................................................................................................................ ................................. 126 xori ........................................................................................................................... ................................. 127 zxb............................................................................................................................ .................................. 128 zxh............................................................................................................................ .................................. 129 5.4 number of instruction execution clock cycles ........ .............................................................. 130 chapter 6 interrupts and exceptions ........................ ........................................................ 134 6.1 interrupt servicing ........................................................................................................ .............. 135 6.1.1 maskabl e inte rrupt ....................................................................................................... ................... 135 6.1.2 non-mask able inte rrupt................................................................................................... ............... 137 6.2 exception processing ....................................................................................................... ......... 138 6.2.1 software except ion....................................................................................................... .................. 138 6.2.2 except ion tr ap ........................................................................................................... ..................... 139 6.2.3 d ebug tr ap ............................................................................................................... ...................... 140 6.3 restoring from interrupt/exception processing ........... .......................................................... 141 6.3.1 restoring from interr upt and software except ion.......................................................................... .. 141 6.3.2 restoring from e xception trap and debug tr ap ............................................................................. .. 142 chapter 7 reset ............................................................................................................. ................. 143 7.1 register status after reset ................................................................................................ ....... 143 7.2 starting up................................................................................................................ ................... 143 chapter 8 pipeline .......................................................................................................... ................ 144 8.1 features ................................................................................................................... .................... 145 8.1.1 non-blocki ng load/st ore .................................................................................................. ............... 146 8.1.2 2-clo ck branc h........................................................................................................... ..................... 147 8.1.3 efficient pi peline proc essing............................................................................................ ............... 148 8.2 pipeline flow during execution of instructions........ .............................................................. 149
11 user?s manual u15943ej3v0um 8.2.1 load inst ructi ons........................................................................................................ .....................149 8.2.2 store in struct ions ....................................................................................................... .....................150 8.2.3 multiply instruct ions.................................................................................................... .....................150 8.2.4 arithmetic oper ation inst ructi ons ........................................................................................ .............152 8.2.5 saturated operat ion instru ctions ......................................................................................... ............153 8.2.6 logical operati on instru ctions ........................................................................................... ..............153 8.2.7 branch in struct ions ...................................................................................................... ...................153 8.2.8 bit manipulat ion instru ctions ............................................................................................ ...............155 8.2.9 special instruct ions ..................................................................................................... ....................155 8.2.10 debug functi on instru ctions............................................................................................. ................160 8.3 pipeline disorder .......................................................................................................... .............. 161 8.3.1 alignm ent haz ard ......................................................................................................... ...................161 8.3.2 referencing execution re sult of load instruct ion......................................................................... .....162 8.3.3 referencing execution resu lt of multiply instru ction ..................................................................... ...163 8.3.4 referencing executi on result of ldsr instru ction for eipc and f epc...........................................164 8.3.5 cautions when creating pr ograms .......................................................................................... ........164 8.4 additional items related to pipeline .......................... ............................................................. . 165 8.4.1 harvard architec ture ..................................................................................................... ..................165 8.4.2 shor t path ............................................................................................................... ........................166 appendix a notes ............................................................................................................ ................ 168 a.1 restriction on conflict between sld instruction and interrupt request .............................. 168 a.1.1 descr ipti on.............................................................................................................. ........................168 a.1.2 counte rmeasur e ........................................................................................................... ..................168 appendix b instruction list................................................................................................ ...... 169 appendix c instruction opcode map ...................... .............................................................. 183 appendix d differences in architecture of v850 cpu and v850e1 cpu ............. 188 appendix e instructions added for v850 es cpu compared with v850 cpu ..... 191 appendix f revision history ................................................................................................ ..... 193 f.1 major revisions in this edition ............................................................................................ .... 193 f.2 history of revisions up to this edition ..................... .............................................................. 1 93
12 user?s manual u15943ej3v0um chapter 1 general real-time control systems are used in a wide range of applications, including: office equipment such as hdds (hard disk drives), ppcs (plain paper copiers), printers, and facsimiles, automobile electronics such as engine contro l systems and abss (antilock braking systems), and factory automation equipment such as nc (numerical control) machine tools and various controllers. the great majority of these systems conventionally employ 8- bit or 16-bit microcontr ollers. however, the performance level of these microcontroll ers has become inadequate in recent year s as control operations have risen in complexity, leading to the development of increasingl y complicated instruction sets and hardware design. as a result, the need has arisen for a new generation of microcontr ollers operable at much higher frequencies to achieve an acceptable level of performance under today?s more demanding requirements. the v850 series of microcontrollers was developed to satisf y this need. this family uses risc architecture that can provide maximum performance with simpler hardware, allowing users to obtain a performance approximately 15 times higher than that of the existing 78k/iii series and 78k/iv series of cisc single-chip micr ocontrollers at a lower total cost. in addition to the basic instructi ons of conventional risc cpus, the v850 series is provided with special instructions such as saturate, bit manipulate, and multiply /divide (executed by a hardware multiplier) instructions, which are especially suited for digital servo control system s. moreover, instruction fo rmats are designed for maximum compiler coding efficiency, allowing the reduction of object code sizes. furthermore, to improve the performance of the v850 se ries, new cpu cores, the v850e1 and v850e2 (under development), are being introduced. these cpu cores are based on the conventional v850 cpu and maintain upward instruction compatibility, but feature enhanced operating fr equencies and pipeline efficiency. another new cpu core, the v850es, was developed for us e in applications that primarily employ 16-bit microcontrollers, and offers the kind of high perfo rmance at a low cost demanded in this field. the v850es is a high-performance, compact cpu core that provides a set of functions (operating frequency, multiplier, dma) optimized for the 16-bit microcontroller ma rket, while maintaining compatibility with the v850e1 cpu with a proven record in 50 mhz class products.
chapter 1 general 13 user?s manual u15943ej3v0um 1.1 features (1) high-performance 32-bit arch itecture for embedded control number of instructions: 83 32-bit general-purpose registers: 32 load/store instructions in long/short format 3-operand instruction 5-stage pipeline of 1 clock cycle per stage hardware interlock on register/flag hazards memory space program space: 64 mb linear (usable area: 16 mb linear space + internal ram area 60 kb) data space: 4 gb linear (2) special instructions saturation operation instructions bit manipulation instructions multiply instructions (on-chip hardware multip lier executing multiplication in 1 or 4 clocks) 16 bits 16 bits 32 bits 32 bits 32 bits 32 bits or 64 bits
chapter 1 general 14 user?s manual u15943ej3v0um 1.2 internal configuration the v850es cpu executes almost all in structions such as address calculatio n, arithmetic and logical operation, and data transfer in one clock by using a 5-stage pipeline. it contains dedicated hardware such as a multiplier (16 16 bits) and a barrel shifter (32 bits/clock) to execute complicated instructions at high speeds. figure 1-1 shows the internal block diagram. figure 1-1. internal blo ck diagram of v850es cpu data cache rom instruction queue multiplier (16 16 32) barrel shifter alu instruction cache program counter general-purpose register system register
15 user?s manual u15943ej3v0um chapter 2 register set the registers can be classified into two types: program registers that can be us ed for general programming, and system registers that can contro l the execution environment. all the registers are 32 bits wide. figure 2-1. registers (a) program registers 0 31 r0 (zero register) r1 (assembler-reserved register) r2 r3 (stack pointer (sp)) r4 (global pointer (gp)) r5 (text pointer (tp)) r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 (element pointer (ep)) r31 (link pointer (lp)) pc (program counter) 0 31 (b) system registers 0 31 eipc (interrupt status saving register) eipsw (interrupt status saving register) fepc (nmi status saving register) fepsw (nmi status saving register) ecr (exception cause register) psw (program status word) ctpc (callt caller status saving register) ctpsw (callt caller status saving register) dbpc (exception/debug trap status saving register) dbpsw (exception/debug trap status saving register) ctbp (callt base pointer) dir (debug interface register)
chapter 2 register set 16 user?s manual u15943ej3v0um 2.1 program registers there are general-purpose regi sters (r0 to r31) and program counter (pc) in the program registers. table 2-1. program registers program register name function description r0 zero register always holds 0. r1 assembler-reserved register used as working register for address generation. r2 address/data variable register (when the real-time os to be used is not using r2) r3 stack pointer (sp) used for stack frame generation when function is called. r4 global pointer (gp) used to a ccess global variable in data area. r5 text pointer (tp) used as register fo r pointing start address of text area (area where program code is placed) r6 to r29 address/data variable registers r30 element pointer (ep) used as base pointer for address generation when memory is accessed. general-purpose register r31 link pointer (lp) used w hen compiler calls function. program counter pc holds instructi on address during program execution. remark for detailed descriptions of r1, r3 to r5, and r 31 used by assembler and c compiler, refer to the ca850 (c compiler package) assembly language user?s manual . (1) general-purpose registers (r0 to r31) thirty-two general-purpose registers, r0 to r31, are provided. all these r egisters can be used for data variable or address variable. however, care must be exercised as follows in using the r0 to r5, r30, and r31 registers. (a) r0, r30 r0 and r30 are implicitly used by instru ctions. r0 is a register that a lways holds 0, and is used for operations and offset 0 addressing. r30 is used as a base pointer when accessing me mory using the sld and sst instructions. (b) r1, r3 to r5, r31 r1, r3 to r5, and r31 are implicitly used by the assembler and c compiler. before using these registers, theref ore, their contents must be saved so that they are not lost. the contents must be restored to the registers a fter the registers have been used. (c) r2 r2 is sometimes used by the real-time os. when the r eal-time os to be used is not using r2, r2 can be used as a variable register.
chapter 2 register set 17 user?s manual u15943ej3v0um (2) program counter (pc) this register holds an instruction addr ess during program execution. the lower 26 bits of this register are valid, and bits 31 to 26 are reserved for future function expansion (fixed to 0). if a carry occurs from bit 25 to bit 26, it is ignored. bit 0 is always fixed to 0, and execution cannot branch to an odd address. figure 2-2. program counter (pc) 31 26 25 1 0 pc 0 initial value 00000000h 000000 (instruction address during execution)
chapter 2 register set 18 user?s manual u15943ej3v0um 2.2 system registers the system registers control the cpu st atus and holds information on interrupts. system registers can be read or writt en by specifying the relevant system r egister number from the following list using a system register load/stor e instruction (ldsr or stsr). table 2-2. system register numbers operand specifiability register no. register name ldsr instruction stsr instruction 0 interrupt status saving register (eipc) { { 1 interrupt status saving register (eipsw) { { 2 nmi status saving register (fepc) { { 3 nmi status saving register (fepsw) { { 4 exception cause register (ecr) { 5 program status word (psw) { { 6 to 15 (numbers reserved for future functi on expansion (operation cannot be guaranteed if accessed)) 16 callt caller status saving register (ctpc) { { 17 callt caller status saving register (ctpsw) { { 18 exception/debug trap status saving register (dbpc) { { 19 exception/debug trap status saving register (dbpsw) { { 20 callt base pointer (ctbp) { { 21 debug interface register (dir) { 22 to 31 (numbers reserved for future functi on expansion (operation cannot be guaranteed if accessed)) caution when returning from interr upt servicing using the reti instruction after setting bit 0 of eipc, fepc, or ctpc to 1 using the ldsr instruction, the value of bit 0 is i gnored (because bit 0 of the pc is fixed to 0). therefore, be sure to set an even number (bit 0 = 0) when setting a value in eipc, fepc, or ctpc. remark o: accessible : inaccessible
chapter 2 register set 19 user?s manual u15943ej3v0um 2.2.1 interrupt status saving registers (eipc, eipsw) two interrupt status saving register s are provided: eipc and eipsw. if a software exception or maskable interrupt occurs, the c ontents of the program counter (pc) are saved to eipc, and the contents of the program status word (psw) are saved to ei psw (if a non-maskable interrupt (nmi) occurs, the contents are saved to nmi stat us saving registers (fepc, fepsw)). except for part of instructions, the address of the instruction next to the one executed when the software exception or maskable interrupt has occurred is saved to the eipc (see table 6-1 interrupt/exception codes ). the current value of the psw is saved to the eipsw. because only one pair of interrupt status saving registers is provided, the contents of these registers must be saved by program when mult iple interrupts are enabled. bits 31 to 26 of the eipc and bits 31 to 8 of the eipsw are reserved for future function expansion (fixed to 0). figure 2-3. interrupt status saving registers (eipc, eipsw) 31 0 eipsw (contents of psw) 8 31 26 25 0 eipc (contents of pc) 000000 000000 000000 000000 0 0 00 initial value 0xxxxxxxh (x: undefined) initial value 000000xxh 0 (x: undefined) 0
chapter 2 register set 20 user?s manual u15943ej3v0um 2.2.2 nmi status saving registers (fepc, fepsw) two nmi status saving registers are provided: fepc and fepsw. if a non-maskable interrupt (nmi) occurs , the contents of the pr ogram counter (pc) are saved to fepc, and the contents of the program status word (psw) are saved to fepsw. except for part of instructions, the address of the instruction next to t he one executed when the nmi has occurred is saved to the fepc (see table 6-1 interrupt/exception codes ). the current value of the psw is saved to the fepsw. because only one pair of nmi status savi ng registers is provided, the contents of these regi sters must be saved by program when multiple interrupts are enabled. bits 31 to 26 of the fepc and bits 31 to 8 of the fepsw are reserved for future function expansion (fixed to 0). figure 2-4. nmi status saving registers (fepc, fepsw) 31 26 25 0 fepc (contents of pc) 31 0 fepsw (contents of psw) 000000 000000 000000 00000 0 0 8 0 00 initial value 0xxxxxxxh (x: undefined) 000000xxh 0 (x: undefined) initial value 0 2.2.3 exception cause register (ecr) the exception cause register (ecr) holds the cause information when an e xception or interrupt occurs. the ecr holds an exception code which ident ifies each interrupt source (see table 6-1 interrupt/exception codes ). this is a read-only register, and therefore, no data can be written to it by using the ldsr instruction. figure 2-5. exception cause register (ecr) 31 0 ecr fecc eicc 16 15 initial value 00000000h bit position bit name function 31 to 16 fecc exception code of non-maskable interrupt (nmi) 15 to 0 eicc exception code of exception or maskable interrupt
chapter 2 register set 21 user?s manual u15943ej3v0um 2.2.4 program status word (psw) the program status word (psw) is a colle ction of flags that indica te the status of the progr am (result of instruction execution) and the st atus of the cpu. if the contents of the bits in this r egister are modified by the ldsr instru ction, the psw will assume the new value immediately after the ldsr instruction has been executed. in setting the id flag to 1, however, interrupt requests are already disabled even while the ld sr instruction is executing. bits 31 to 8 are reserved for future function expansion (fixed to 0). figure 2-6. program status word (psw) (1/2) 31 87 6 5 4 3 2 1 0 psw n p s a t e p i d o v sz c y initial value 00000020h 000000 000000 000000 0 0 000 0 bit position flag name function 7 np indicates that non-maskable interrupt (nmi) proce ssing is in progress. this flag is set to 1 when nmi request is acknowledged, and mu ltiple interrupts are disabled. 0: nmi processing is not in progress 1: nmi processing is in progress 6 ep indicates that exception processing is in progr ess. this flag is set to 1 when an exception occurs. even when this bit is set, interrupt requests can be acknowledged. 0: exception processing is not in progress 1: exception processing is in progress 5 id indicates whether maskable inte rrupt request can be acknowledged. 0: interrupt can be acknowledged 1: interrupt cannot be acknowledged 4 sat note indicates that an overflow has occurred in a sa turate operation and the result is saturated. this is a cumulative flag. when the result is saturated, the flag is set to 1 and is not cleared to 0 even if the next result does not saturate . to clear this flag to 0, use the ldsr instruction. this flag is neither set to 1 nor cleared to 0 by execution of arithmetic operation instruction. 0: not saturated 1: saturated 3 cy indicates whether carry or borrow occurred as a result of the operation. 0: carry or borrow did not occur 1: carry or borrow occurred 2 ov note indicates whether overflow occurred as a result of the operation. 0: overflow did not occur 1: overflow occurred 1 s note indicates whether the result of the operation is negative. 0: result is positive or zero 1: result is negative 0 z indicates whether the result of the operation is zero. 0: result is not zero 1: result is zero note in the case of saturate instruct ions, the sat, s, and ov flags will be se t according to the result of the operation as shown in the table below. note that the sat flag is set to 1 only when the ov flag has been set to 1 during saturate operation.
chapter 2 register set 22 user?s manual u15943ej3v0um figure 2-6. program status word (psw) (2/2) status of flag status of operation result sat ov s operation result of saturation processing maximum positive value is exceeded 1 1 0 7fffffffh maximum negative value is exceeded 1 1 1 80000000h positive (not exceeding maximum value) holds the value before 0 0 operation result negative (not exceeding maximum value) operation 1 2.2.5 callt caller status saving registers (ctpc, ctpsw) two callt caller status saving regist ers are provided: ctpc and ctpsw. if a callt instruction is executed, t he contents of the program counter (pc) are saved to ctpc, and the contents of the program status word (psw) are saved to ctpsw. the contents saved to the ctpc ar e the address of the instruction next to the callt instruction. the current value of the psw is saved to the ctpsw. bits 31 to 26 of the ctpc and bits 31 to 8 of the ctpsw are reserved for future function expansion (fixed to 0). figure 2-7. callt caller status saving registers (ctpc, ctpsw) 31 26 25 0 ctpc (contents of pc) 31 0 ctpsw (contents of psw) 000000 000000 000000 000000 0 0 8 00 initial value 0xxxxxxxh (x: undefined) 000000xxh 0 initial value (x: undefined) 0
chapter 2 register set 23 user?s manual u15943ej3v0um 2.2.6 exception/debug trap status saving registers (dbpc, dbpsw) two exception/debug trap status saving regi sters are provided: dbpc and dbpsw. if an exception trap or debug trap occurs, the contents of the progr am counter (pc) are saved to dbpc, and the contents of the program status word (psw) are saved to dbpsw. the contents saved to the dbpc are the address of the instruction next to the one executed w hen the exception trap or debug trap has occurred. the current value of the psw is saved to the dbpsw. bits 31 to 26 of the dbpc and bits 31 to 8 of the dbpsw are reserved for future function expansion (fixed to 0). figure 2-8. exception/debug trap stat us saving registers (dbpc, dbpsw) 31 26 25 0 dbpc (contents of pc) 31 dbpsw 000000 000000 000000 00000 0 0 0 (contents of psw) 0 8 00 initial value 0xxxxxxxh (x: undefined) 000000xxh 0 initial value (x: undefined) 0 2.2.7 callt base pointer (ctbp) the callt base pointer (ctbp) is used to specify a table address and to generate a target address (bit 0 is fixed to 0). bits 31 to 26 are reserved for future function expansion (fixed to 0). figure 2-9. callt base pointer (ctbp) 31 26 25 0 ctbp (base address) 000000 0 initial value 0xxxxxxxh (x: undefined)
chapter 2 register set 24 user?s manual u15943ej3v0um 2.2.8 debug interface register (dir) the debug interface register (dir) indicates w hether the status is normal mode or debug mode. the dm bit is set to 1 when an exception trap occurs or when the dbtrap instruction is executed, and is cleared to 0 when the dbret instruction is executed. the contents of the dir r egister can be read by setting them to a general-purpose register using the stsr instruction. the dir regi ster cannot be written. bits 31 to 1 are reserved for future function expansion (fixed to 0). figure 2-10. debug interface register (dir) 31 dir 000000 000000 00000 0 0 0 d m 00 1 00 initial value 00000000h 00000000 bit position bit name function 0 dm set to 1 when an exception trap occurs or when the dbtrap instruction is executed, and cleared to 0 when the dbret instruction is executed. 0: normal mode 1: debug mode
25 user?s manual u15943ej3v0um chapter 3 data type 3.1 data format the following data types are supported (see 3.2 data representation ). ? integer (32, 16, 8 bits) ? unsigned integer (32, 16, 8 bits) ? bit three types of data lengths: word (32 bi ts), halfword (16 bits), and byte (8 bi ts) are supported. byte 0 of any data is always the least significant byte (this is called little endian) and shown at the rightmost position in figures throughout this manual. the following paragraphs describe the data format where data of fixed length is in memory. (1) word a word is 4-byte (32-bit) contiguous data that starts fr om any word boundary note . each bit is assigned a number from 0 to 31. the lsb (least significant bit) is bit 0 and the msb (most significant bit) is bit 31. a word is specified by its address a (with the 2 lowest bits fixed to 0 when misalign access is disabled note ), and occupies 4 bytes, a, a+1, a+2, and a+3. note when misalign access is enabled, any byte boundary c an be accessed whether access is in halfword or word units. see 3.3 data alignment . 31 24 23 16 15 7 0 data 8 address a a+1 a+2 a+3 l b s m b s
chapter 3 data type 26 26 user?s manual u15943ej3v0um (2) halfword a halfword is 2-byte (16-bit) contiguous data that starts fr om any halfword boundary note . each bit is assigned a number from 0 to 15. the lsb is bit 0 and the msb is bit 15. a halfword is specified by its address a (with the lowest bit fixed to 0 note ), and occupies 2 bytes, a and a+1. note when misalign access is enabled, any byte boundary can be accessed whether access is in halfword or word units. see 3.3 data alignment . 15 7 0 data 8 address a a+1 m b s l b s (3) byte a byte is 8-bit contiguous data t hat starts from any byte boundary note . each bit is assigned a number from 0 to 7. the lsb is bit 0 and the msb is bit 7. a byte is specified by its address a. note when misalign access is enabled, any byte boundary can be accessed whether access is in halfword or word units. see 3.3 data alignment . 7 0 data address a l b s m b s (4) bit a bit is 1-bit data at the nth bit position in 8-bit data that starts from any byte boundary note . a bit is specified by its address a and bit number n. note when misalign access is enabled, any byte boundary can be accessed whether access is in halfword or word units. see 3.3 data alignment . 7 byte of address a ... 0 address a bit number n data
chapter 3 data type 27 27 user?s manual u15943ej3v0um 3.2 data representation 3.2.1 integer an integer is expressed as a binary num ber of 2?s complement and is 32, 16, or 8 bits long. regardless of its length, the bit 0 of an integer is the least significant bit. the higher t he bit number, the more significant the bit. because 2?s complement is used, the most significant bit is used as a sign bit. the integer range of each dat a length is as follows. ? word (32 bits): ?2, 147,483,648 to +2,147,483,647 ? halfword (16 bits): ?32,768 to +32,767 ? byte (8 bits): ?128 to +127 3.2.2 unsigned integer while an integer is data that can take either a positive or a negat ive value, an unsigned integer is an integer that is not negative. like an integer, an unsigned integer is also expressed as 2?s co mplement and is 32, 16, or 8 bits long. regardless of its length, bit 0 of an uns igned integer is the least significant bi t, and the higher the bit number, the more significant the bit. however, no sign bit is used. the unsigned integer range of eac h data length is as follows. ? word (32 bits): 0 to 4,294,967,295 ? halfword (16 bits): 0 to 65,535 ? byte (8 bits): 0 to 255 3.2.3 bit 1-bit data that can take a value of 0 (cleared) or 1 (set) can be handled as a bit data. bit manipulation can be performed only to 1-byte data in the memo ry space in the following four ways: ? set1 ? clr1 ? not1 ? tst1 3.3 data alignment due to the incorporation of a misalign function, data that is a llocated to the memory can be placed at any address regardless of the data format (word data, halfword data). however, if word data is not aligned at a word boundary (the lower 2 bits of the address are 0), or halfword data is not aligned at a halfw ord boundary (the lowest bit of the address is 0), one or more surplus bus cycles are gener ated, which lowers the bus efficiency.
28 user?s manual u15943ej3v0um chapter 4 address space the v850es cpu supports a 4 gb linear address space. both memory and i/o are mapped to this address space (memory-mapped i/o). the v850es cpu outputs 32-bit addresse s to the memory and i/o. the maximum address is 2 32 ? 1. byte data allocated at each address is defined with bit 0 as lsb and bit 7 as m sb. in regards to multiple-byte data, the byte with the lowe st address value is defined to have the lsb and the byte with the highest address value is defined to have the msb (little endian). data consisting of 2 bytes is called a hal fword, and 4-byte data is called a word. in this user ? s manual, data consisting of 2 or more bytes is illustrated as shown below, with the lower address shown on the right and the higher address on the left. 31 24 23 16 15 7 0 8 data address data address data address a a+1 a+2 a+3 15 7 0 8 a a+1 7 0 a word at address a ............................................................................................ halfword at address a ............................................................................................................................... ....... byte at address a .......
chapter 4 address space 29 user?s manual u15943ej3v0um 4.1 memory map the v850es cpu employs a 32-bit architecture and supports a linear address space (data area) of up to 4 gb for operand addressing (data access). it supports a linear address space (program area) of up to 64 mb for instruction addressing. however, areas usable as program area are a linear address space of up to 16 mb and the internal ram area (60 kb max.). figure 4-1 shows the memory map. figure 4-1. memory map (a) address space (b) program area 00000000h 03ffffffh 04000000h ffffffffh data area (4 gb linear) program area (64 mb linear) 3ffffffh 3fff000h 3ffefffh 0000000h 64 mb 3ff0000h 3feffffh 1000000h 0ffffffh 16 mb 60 kb internal ram area peripheral i/o area (4 kb) reserved external memory area internal rom area remark : use as program area is prohibited
chapter 4 address space 30 user?s manual u15943ej3v0um 4.2 addressing mode the cpu generates two types of addr esses: instruction addresses used for instruction fetch and branch operations; and operand addresses used for data access. 4.2.1 instruction address an instruction address is determined by the contents of t he program counter (pc) , and is automatically incremented (+2) according to the number of bytes of an instruction to be fetched each time an instruction has been executed. when a branch inst ruction is executed, the br anch destination address is loaded into the pc using one of the following two addressing modes: (1) relative addressing (pc relative) the signed 9- or 22-bit data of an instruction code (displacement: disp ) is added to the value of the program counter (pc). at this time, the displacement is treat ed as 2?s complement data with bits 8 and 21 serving as sign bits (s). this addressing is used for jarl disp22, r eg2, jr disp22, and bcond disp9 instructions. figure 4-2. relative addressing (1/2) (a) jarl disp22, reg2 instru ction, jr disp22 instruction 31 25 0 0pc 00000 31 22 0 sign extension s + 21 0 disp22 memory to be manipulated 31 25 0 0pc 00000 26 26 0 0
chapter 4 address space 31 user?s manual u15943ej3v0um figure 4-2. relative addressing (2/2) (b) bcond disp9 instruction 31 25 0 0pc 00000 31 0 sign extension s + 0 disp9 memory to be manipulated 31 25 0 0pc 00000 26 26 8 9 0 0 (2) register addressing (r egister indirect) the contents of a general-pur pose register (reg1) specif ied by an instruction are transferred to the program counter (pc). this addressing is applied to the jmp [reg1] instruction. figure 4-3. register addressing (jmp [reg1] instruction) 31 0 reg1 memory to be manipulated 31 25 0 0pc 00000 26 0
chapter 4 address space 32 user?s manual u15943ej3v0um 4.2.2 operand address when an instruction is execut ed, the register or memory area to be a ccessed is specified in one of the following four addressing modes: (1) register addressing the general-purpose register or system register specifi ed in the general-purpose regist er specification field is accessed as operand. this addressing mode applies to instructions usi ng the operand format reg1, r eg2, reg3, or regid. (2) immediate addressing the 5-bit or 16-bit data for manipulation is contained in the instruction code. this addressing mode applies to instructions usi ng the operand format imm5, imm16, vector, or cccc. remark vector: operand that is 5-bit imm ediate data to specify trap vector (00h to 1fh), and is used in trap instruction. cccc: operand consisting of 4- bit data used in cmov, sasf, and setf instructions to specify condition code. assigned as part of instruct ion code as 5-bit immediate data by appending 1- bit 0 above highest bit. (3) based addressing the following two types of based addressing are supported: (a) type 1 the address of the data memory location to be access ed is determined by adding the value in the specified general-purpose register (reg1) to the 16-bit displacem ent value (disp16) contained in the instruction code. this addressing mode applies to instruct ions using the operand format disp16 [reg1]. figure 4-4. based addressing (type 1) 31 0 reg1 memory to be manipulated 31 0 sign extension disp16 + 15 16
chapter 4 address space 33 user?s manual u15943ej3v0um (b) type 2 the address of the data memory location to be access ed is determined by adding t he value in the element pointer (r30) to the 7- or 8-bit di splacement value (disp7, disp8). this addressing mode applies to sld and sst instructions. figure 4-5. based addressing (type 2) 31 0 r30 (element pointer) memory to be manipulated 31 0 0 (zero extension) disp8 or disp7 + 7 8 remark byte access: disp7 halfword access and word access: disp8 (4) bit addressing this addressing is used to access 1 bit (specified with bit #3 of 3-bit data) among 1 byte of the memory space to be manipulated by using an operand addre ss which is the sum of the cont ents of a general- purpose register (reg1) and a 16-bit displacement (disp16) sign-extended to a word length. this addressing mode applies only to bit manipulate instructions. figure 4-6. bit addressing 31 0 reg1 memory to be manipulated 31 0 sign extension disp16 + 15 16 n remark n: bit position specified with 3-bit data (bit#3) (n = 0 to 7)
34 user?s manual u15943ej3v0um chapter 5 instruction 5.1 instruction format there are two types of instruction formats: 16-bit and 32-bit. the 16-bit format instructions include binary operation, control, and conditi onal branch instructions, and the 32-bit format instructions include load/store, jump, and instructions that handle 16-bit immediate data. an instruction is actually stored in memory as follows: lower bytes of instruction (including bit 0) lower address higher bytes of instruction (including bit 15 or bit 31) higher address caution some instructions have an unused field (rfu). this field is reserved for future expansion and must be fixed to 0. (1) reg-reg instruction (format i) a 16-bit instruction format having a 6-bit opcode field and two general-purpose register specification fields. 15 11 10 5 4 0 reg2 opcode reg1 (2) imm-reg instruction (format ii) a 16-bit instruction format having a 6-bit opcode field, 5-bit immediate field, and a general-purpose register specification field. 15 11 10 5 4 0 reg2 opcode imm
chapter 5 instruction 35 user?s manual u15943ej3v0um (3) conditional branch instruction (format iii) a 16-bit instruction format having a 4-bit opcode field, 4- bit condition code field, and an 8-bit displacement field. 15 11 10 6 4 0 disp opcode cond disp 3 7 (4) 16-bit load/store instruction (format iv) a 16-bit instruction format having a 4-bit opcode field, a general-purpose register specif ication field, and a 7-bit displacement field (or 6-bit displacement field + 1-bit sub-opcode field). 15 11 10 6 0 reg2 opcode disp disp/sub-opcode 1 7 a 16-bit instruction format having a 7-bit opcode field, a general-purpose register specif ication field, and a 4-bit displacement field. 15 11 10 4 0 reg2 opcode disp 3 (5) jump instruction (format v) a 32-bit instruction format having a 5-bit opcode field, a general-purpose register specif ication field, and a 22-bit displacement field. 15 11 10 16 opcode disp 0 031 reg2 17 65
chapter 5 instruction 36 user?s manual u15943ej3v0um (6) 3-operand instruction (format vi) a 32-bit instruction format having a 6-bit opcode field, two general-purpose register s pecification fields, and a 16- bit immediate field. 15 11 10 16 opcode imm 031 reg2 4 5 reg1 (7) 32-bit load/store instruction (format vii) a 32-bit instruction format having a 6-bit opcode field, two general-purpose register s pecification fields, and a 16- bit displacement field (or 15-bit displa cement field + 1-bit sub-opcode field). 15 11 10 16 opcode disp 031 reg2 4 5 reg1 disp/sub-opcode 17 (8) bit manipulation instruction (format viii) a 32-bit instruction format having a 6-bit opcode field, 2-bi t sub-opcode field, 3-bit bit s pecification field, a general- purpose register specification field, and a 16-bit displacement field. 15 11 10 16 opcode disp 031 bit # 4 5 reg1 sub 14 13 (9) extended instruction format 1 (format ix) a 32-bit instruction format having a 6-bit opcode field, 6-bit sub-opcode field, and two general-purpose register specification fields (one field may be register num ber field (regid) or condition code field (cond)). 15 11 10 16 17 opcode sub-opcode 031 reg2 4 5 reg1/regid/cond rfu rfu 27 26 20 21 0
chapter 5 instruction 37 user?s manual u15943ej3v0um (10) extended instruction format 2 (format x) a 32-bit instruction format having a 6-bit opcode field and 6-bit sub-opcode field. 15 11 10 16 17 opcode sub-opcode 031 rfu 4 5 rfu rfu 27 26 20 21 13 12 rfu/sub-opcode rfu/imm/vector 0 (11) extended instruction format 3 (format xi) a 32-bit instruction format having a 6-bit opcode field, 6-bit and 1-bit sub-opcode fi eld, and three general-purpose register specification fields. 15 11 10 16 opcode sub-opcode 031 reg2 4 5 rfu reg3 27 26 20 21 0 17 18 sub-opcode reg1 (12) extended instruction format 4 (format xii) a 32-bit instruction format having a 6-bit opcode field, 4- bit and 1-bit sub-opcode field, 10-bit immediate field, and two general-purpose register specification fields. 15 11 10 16 opcode sub-opcode 031 reg2 4 5 imm (high) reg3 27 26 22 0 17 18 imm (low) 23 sub-opcode (13) stack manipulation instruction 1 (format xiii) a 32-bit instruction format having a 5-bit opcode field, 5- bit immediate field, 12-bit register list field, and one general-purpose register s pecification field (or 5-bit sub-opcode field). 15 11 10 16 opcode reg2/sub-opcode 031 rfu 65 list 20 imm 121
chapter 5 instruction 38 user?s manual u15943ej3v0um 5.2 outline of instructions (1) load instructions transfer data from memory to a register. the following instructions (mnemonics) are provided. (a) ld instructions ? ld.b: load byte ? ld.bu: load byte unsigned ? ld.h: load halfword ? ld.hu: load halfword unsigned ? ld.w: load word (b) sld instructions ? sld.b: short format load byte ? sld.bu: short format load byte unsigned ? sld.h: short format load halfword ? sld.hu: short format load halfword unsigned ? sld.w: short format load word (2) store instructions transfer data from register to a memory. the following instructions (mnemonics) are provided. (a) st instructions ? st.b: store byte ? st.h: store halfword ? st.w: store word (b) sst instructions ? sst.b: short format store byte ? sst.h: short format store halfword ? sst.w: short format store word (3) multiply instructions execute multiply processing in 1 to 5 clocks with on-ch ip hardware multiplier. the following instructions (mnemonics) are provided. ? mul: multiply word ? mulh: multiply halfword ? mulhi: multiply halfword immediate ? mulu: multiply word unsigned
chapter 5 instruction 39 user?s manual u15943ej3v0um (4) arithmetic operation instructions add, subtract, divide, transfer, or compare data between registers. t he following instructions (mnemonics) are provided. ? add: add ? addi: add immediate ? cmov: conditional move ? cmp: compare ? div: divide word ? divh: divide halfword ? divhu: divide halfword unsigned ? divu: divide word unsigned ? mov: move ? movea: move effective address ? movhi: move high halfword ? sasf: shift and set flag condition ? setf: set flag condition ? sub: subtract ? subr: subtract reverse (5) saturated operation instructions execute saturation addition and subtraction. if the re sult of the operation exc eeds the maximum positive value (7fffffffh), 7fffffffh is returned. if the result of the operat ion exceeds the maximum negative value (80000000h), 80000000h is returned. the follo wing instructions (mnemonics) are provided. ? satadd: saturated add ? satsub: saturated subtract ? satsubi: saturated subtract immediate ? satsubr: saturated subtract reverse (6) logical operation instructions these instructions include logical operation and shift inst ructions. the shift instru ctions include arithmetic shift and logical shift instructions. operands can be shi fted by two or more bit positions in one clock cycle by the on-chip barrel shifter. the followi ng instructions (mnemonics) are provided. ? and: and ? andi: and immediate ? bsh: byte swap halfword ? bsw: byte swap word ? hsw: halfword swap word ? not: not ? or: or ? ori: or immediate ? sar: shift arithmetic right ? shl: shift logical left ? shr: shift logical right ? sxb: sign extend byte ? sxh: sign extend halfword
chapter 5 instruction 40 user?s manual u15943ej3v0um ? tst: test ? xor: exclusive or ? xori: exclusive or immediate ? zxb: zero extend byte ? zxh: zero extend halfword (7) branch instructions these instructions include unconditional branch inst ructions (jarl, jmp, jr) and conditional branch instruction (bcond) which alters the control depending on the status of flags. program control can be transferred to the address specified by a branch instruction. the fo llowing instructions (mnemonics) are provided. ? bcond (bc, be, bge, bgt, bh, bl, ble, blt, bn, bnc, bne, bnh, bnl, bnv, bnz, bp, br, bsa, bv, bz): branch on condition code ? jarl: jump and register link ? jmp: jump register ? jr: jump relative (8) bit manipulation instructions execute a logical operation to the s pecified bit data in memory. the fo llowing instructions (mnemonics) are provided. ? clr1: clear bit ? not1: not bit ? set1: set bit ? tst1: test bit (9) special instructions these instructions are in structions not included in the categories of instruct ions described above. the following instructions (mnemonics) are provided. ? callt: call with table look up ? ctret: return from callt ? di: disable interrupt ? dispose: function dispose ? ei: enable interrupt ? halt: halt ? ldsr: load system register ? nop: no operation ? prepare: function prepare ? reti: return from trap or interrupt ? stsr: store system register ? switch: jump with table look up ? trap: trap
chapter 5 instruction 41 user?s manual u15943ej3v0um (10) debug function instructions these instructions are in structions reserved for debug function. t he following instructions (mnemonics) are provided. ? dbret: return from debug trap ? dbtrap: debug trap
chapter 5 instruction 42 user?s manual u15943ej3v0um 5.3 instruction set in this section, mnemonic of each instructi on is described divided into the following items. ? instruction format: indicates the description and operand of the instruct ion (for symbols, see table 5-1 ). ? operation: indicates t he function of the instru ction (for symbols, see table 5-2 ). ? format: indicates the instruction format (see 5.1 instruction format ). ? opcode: indicates the bit field of the instruction opcode (for symbols, see table 5-3 ). ? flag: indicates the operation of the flag which is altered afte r executing the instruction. 0 indicates clear (reset), 1 indicates set, and ? indicates no change. ? explanation: explains the oper ation of the instruction. ? remark: explains the supplementar y information of the instruction. ? caution: indicates the cautions. table 5-1. conventions of instruction format symbol meaning reg1 general-purpose register (used as source register) reg2 g eneral-purpose register (mainly used as destination register. some are also used as source registers) reg3 g eneral-purpose register (mainly used as remainder of division results or higher 32 bits of multiply results) bit#3 3-bit data for specifying bit number imm -bit immediate data disp -bit displacement data regid system register number vector 5-bit data for trap vector (00h to1fh) specification cccc 4-bit data for condition code specification sp stack pointer (r3) ep element pointer (r30) list lists of registers ( is a maximum number of registers) table 5-2. conventions of operation (1/2) symbol meaning assignment gr [ ] general-purpose register sr [ ] system register zero-extend (n) zero-extends n to word sign-extend (n) sign-extends n to word load-memory (a, b) reads data of size b from address a store-memory (a, b, c) writes data b of size c to address a load-memory-bit (a, b) reads bit b from address a store-memory-bit (a, b, c) writes c to bit b of address a
chapter 5 instruction 43 user?s manual u15943ej3v0um table 5-2. conventions of operation (2/2) symbol meaning saturated (n) performs saturation processing of n. if n > 7fffffffh as result of calculation, n = 7fffffffh. if n < 80000000h as result of calculation, n = 80000000h. result reflects result on flag byte byte (8 bits) halfword halfword (16 bits) word word (32 bits) + add ? subtract || bit concatenation multiply divide % remainder of division results and and or or xor exclusive or not logical negate logically shift left by logical left shift logically shift right by logical right shift arithmetically shift right by arithmetic right shift table 5-3. conventions of opcode symbol meaning r 1-bit data of code specifying reg1 or regid r 1-bit data of code specifying reg2 w 1-bit data of code specifying reg3 d 1-bit data of displacement i 1-bit data of immediate (indica tes higher bits of immediate) i 1-bit data of immediate cccc 4-bit data for condition code specification cccc 4-bit data for condition code spec ification of bcond instruction bbb 3-bit data for bit number specification l 1-bit data of code specifying progr am register in register list
chapter 5 instruction 44 user?s manual u15943ej3v0um add register/immediate add add instruction format (1) add reg1, reg2 (2) add imm5, reg2 operation (1) gr [reg2] gr [reg2] + gr [reg1] (2) gr [reg2] gr [reg2] + sign-extend (imm5) format (1) format i (2) format ii opcode 15 0 (1) rrrrr001110rrrrr 15 0 (2) rrrrr010010iiiii flag cy 1 if a carry occurs from msb; otherwise, 0. ov 1 if overflow occurs; otherwise, 0. s 1 if the operation result is negative; otherwise, 0. z 1 if the operation resu lt is 0; otherwise 0. sat ? explanation (1) adds the word data of general-purpose register reg1 to the word data of general-purpose register reg2, and stores the result to general-purpose regist er reg2. the data of general- purpose register reg1 is not affected. (2) adds 5-bit immediate data, sign-extended to word length, to the word data of general- purpose register reg2, and st ores the result to general -purpose register reg2.
chapter 5 instruction 45 user?s manual u15943ej3v0um add immediate addi add immediate instruction format addi imm16, reg1, reg2 operation gr [reg2] gr [reg1] + sign-extend (imm16) format format vi opcode 15 0 31 16 rrrrr110000rrrrr iiiiiiiiiiiiiiii flag cy 1 if a carry occurs from msb; otherwise, 0. ov 1 if overflow occurs; otherwise, 0. s 1 if the operation result is negative; otherwise, 0. z 1 if the operation resu lt is 0; otherwise 0. sat ? explanation adds 16-bit immediate data, si gn-extended to word length, to the word data of general-purpose register reg1, and stores the result to general-purpose regist er reg2. the data of general- purpose register reg1 is not affected.
chapter 5 instruction 46 user?s manual u15943ej3v0um and and and instruction format and reg1, reg2 operation gr [reg2] gr [reg2] and gr [reg1] format format i opcode 15 0 rrrrr001010rrrrr flag cy ? ov 0 s 1 if the mbs of the word data of t he operation result is 1; otherwise, 0. z 1 if the operation resu lt is 0; otherwise 0. sat ? explanation ands the word data of general -purpose register reg2 with t he word data of general-purpose register reg1, and stores the result to general-purpose regist er reg2. the data of general- purpose register reg1 is not affected.
chapter 5 instruction 47 user?s manual u15943ej3v0um and immediate andi and immediate instruction format andi imm16, reg1, reg2 operation gr [reg2] gr [reg1] and zero-extend (imm16) format format vi opcode 15 0 31 16 rrrrr110110rrrrr iiiiiiiiiiiiiiii flag cy ? ov 0 s 1 if the msb of the word data of t he operation result is 1; otherwise, 0. z 1 if the operation resu lt is 0; otherwise 0. sat ? explanation ands the word data of general -purpose register r eg1 with the value of the 16-bit immediate data, zero-extended to word length, and stores the result to general -purpose register reg2. the data of general-purpose regist er reg1 is not affected.
chapter 5 instruction 48 user?s manual u15943ej3v0um branch on condition code with 9-bit displacement bcond branch on condition code instruction format bcond disp9 operation if conditions are satisfied then pc pc + sign-extend (disp9) format format iii opcode 15 0 ddddd1011dddcccc dddddddd is the higher 8 bits of disp9. flag cy ? ov ? s ? z ? sat ? explanation tests each flag of psw specified by the instru ction. branches if a specified condition is satisfied; otherwise, executes t he next instruction. the branch destination pc holds the sum of the current pc value and 9-bit displacement, wh ich is 8-bit immediate shifted 1 bit and sign- extended to word length. remark bit 0 of the 9-bit displacement is masked to 0. the current pc value used for calculation is the address of the first byte of this instruction. if the displacement value is 0, therefore, the branch destination is this instruction itself.
chapter 5 instruction 49 user?s manual u15943ej3v0um table 5-4. bcond instructions instruction condition code (cccc) status of flag branch condition bge 1110 (s xor ov) = 0 greater than or equal signed bgt 1111 ( (s xor ov) or z) = 0 greater than signed ble 0111 ( (s xor ov) or z) = 1 less than or equal signed signed integer blt 0110 (s xor ov) = 1 less than signed bh 1011 (cy or z) = 0 higher (greater than) bl 0001 cy = 1 lower (less than) bnh 0011 (cy or z) = 1 not higher (less than or equal) unsigned integer bnl 1001 cy = 0 not lower (greater than or equal) be 0010 z = 1 equal common bne 1010 z = 0 not equal bc 0001 cy = 1 carry bn 0100 s = 1 negative bnc 1001 cy = 0 no carry bnv 1000 ov = 0 no overflow bnz 1010 z = 0 not zero bp 1100 s = 0 positive br 0101 ? always (unconditional) bsa 1101 sat = 1 saturated bv 0000 ov = 1 overflow others bz 0010 z = 1 zero caution if executing a conditional branch instruction of a si gned integer (bge, bgt, ble, or blt) when the sat flag is set to 1 as a result of executing a satura ted operation instruction, t he branch condition loses its meaning. in ordinary operations, if an over flow occurs, the s flag is inverted (0
chapter 5 instruction 50 user?s manual u15943ej3v0um byte swap halfword bsh byte swap halfword instruction format bsh reg2, reg3 operation gr [reg3] gr [reg2] (23:16) || gr [reg2] (31:24) || gr [reg2] (7:0) || gr [reg2] (15:8) format format xii opcode 15 0 31 16 rrrrr11111100000 wwwww01101000010 flag cy 1 if one or more bytes in resu lt lower halfword is 0; otherwise 0. ov 0 s 1 if the msb of the word data of t he operation result is 1; otherwise, 0. z 1 if the lower halfword data of the operation result is 0; otherwise, 0. sat ? explanation endian translation.
chapter 5 instruction 51 user?s manual u15943ej3v0um byte swap word bsw byte swap word instruction format bsw reg2, reg3 operation gr [reg3] gr [reg2] (7:0) || gr [reg2] (15:8) || gr [reg2] (23:16) || gr [reg2] (31:24) format format xii opcode 15 0 31 16 rrrrr11111100000 wwwww01101000000 flag cy 1 if one or more bytes in result word is 0; otherwise 0. ov 0 s 1 if the msb of the word data of t he operation result is 1; otherwise, 0. z 1 if the word data of the operat ion result is 0; otherwise, 0. sat ? explanation endian translation.
chapter 5 instruction 52 user?s manual u15943ej3v0um call with table look up callt call with table look up instruction format callt imm6 operation ctpc pc + 2 (return pc) ctpsw psw adr ctbp + zero-extend (imm6 l ogically shift left by 1) pc ctbp + zero-extend (load-memory (adr, halfword)) format format ii opcode 15 0 0000001000iiiiii flag cy ? ov ? s ? z ? sat ? explanation saves the restore pc and psw to ctpc and ctpsw. adds the ctbp and data of imm6, logically shifted left by 1 and zero-extended to word length, to generat e a 32-bit table entry address. then load the halfwor d entry data, zero-extended to word length, and adds the data and ctbp to generate a 32-bit target address. then jump to a target address. caution if an interrupt is generated during in struction execution, the execution of t hat instruction may stop after the end of the read/wr ite cycle. execution is resumed after returning from the interrupt.
chapter 5 instruction 53 user?s manual u15943ej3v0um clear bit clr1 clear bit instruction format (1) clr1 bit#3, disp16 [reg1] (2) clr1 reg2, [reg1] operation (1) adr gr [reg1] + sign-extend (disp16) z flag not (load-memory-bit (adr, bit#3)) store-memory-bit (adr, bit#3, 0) (2) adr gr [reg1] z flag not (load-memory-bit (adr, reg2)) store-memory-bit (adr, reg2, 0) format (1) format viii (2) format ix opcode 15 0 31 16 (1) 10bbb111110rrrrr dddddddddddddddd 15 0 31 16 (2) rrrrr111111rrrrr 0000000011100100 flag cy ? ov ? s ? z 1 if bit specified by operands = 0, 0 if bit specified by operands = 1 sat ? explanation (1) adds the data of general- purpose register reg1 to the 16- bit displacement, sign-extended to word length, to generate a 32-bit address. then reads the byte dat a referenced by the generated address, clears the bit specified by the bit number of 3 bits, and rewrites the original address. (2) reads the data of general- purpose register reg1 to generat e a 32-bit address. then reads the byte data referenced by t he generated address, clears the bi t specified by the data of lower 3 bits of reg2, and rewr ites the original address. remark the z flag of the psw indicates whether the specified bit was a 0 or 1 before this instruction is executed. it does not indicate the content of the s pecified bit after this instruction has been executed.
chapter 5 instruction 54 user?s manual u15943ej3v0um conditional move cmov conditional move instruction format (1) cmov cccc, reg1, reg2, reg3 (2) cmov cccc, imm5, reg2, reg3 operation (1) if conditions are satisfied then gr [reg3] gr [reg1] else gr [reg3] gr [reg2] (2) if conditions are satisfied then gr [reg3] sign-extend (imm5) else gr [reg3] gr [reg2] format (1) format xi (2) format xii opcode 15 0 31 16 (1) rrrrr111111rrrrr wwwww011001cccc0 15 0 31 16 (2) rrrrr111111iiiii wwwww011000cccc0 flag cy ? ov ? s ? z ? sat ? explanation (1) the general-purpose register reg3 is set to the data of general-purpos e register reg1 if a condition specified by condition code ?cccc? is satisfied; otherwise, set to the data of general-purpose register reg2. one of the codes shown in table 5-5 condition codes should be specified as the condition code ?cccc?. (2) the general-purpose register reg3 is set to the data of 5-bit imm ediate, sign-extended to word length, if a condition s pecified by condition code ?cccc? is satisfied; otherwise, set to the data of general-purpose register reg2. one of the codes shown in table 5-5 condition codes should be specified as the condition code ?cccc?. remark see setf instruction.
chapter 5 instruction 55 user?s manual u15943ej3v0um compare register/immediate (5-bit) cmp compare instruction format (1) cmp reg1, reg2 (2) cmp imm5, reg2 operation (1) result gr [reg2] ? gr [reg1] (2) result gr [reg2] ? sign-extend (imm5) format (1) format i (2) format ii opcode 15 0 (1) rrrrr001111rrrrr 15 0 (2) rrrrr010011iiiii flag cy 1 if a borrow to msb occurs; otherwise, 0. ov 1 if overflow occurs; otherwise 0. s 1 if the operation result is negative; otherwise, 0. z 1 if the operation resu lt is 0; otherwise, 0. sat ? explanation (1) compares the word data of general-purpose regi ster reg2 with the wo rd data of general- purpose register reg1, and indicate s the result by using the flags of psw. to compare, the contents of general-purpos e register reg1 are subtracted from the word data of general- purpose register reg2. t he data of general-purpose regi sters reg1 and reg2 are not affected. (2) compares the word data of general-purpose regi ster reg2 with 5-bit immediate data, sign- extended to word length, and indicates the result by using the flags of psw. to compare, the contents of the sign-ext ended immediate data is subtract ed from the word data of general-purpose register reg2. the data of general-pur pose register reg2 is not affected.
chapter 5 instruction 56 user?s manual u15943ej3v0um return from callt ctret return from callt instruction format ctret operation pc ctpc psw ctpsw format format x opcode 15 0 31 16 0000011111100000 0000000101000100 flag cy value read from ctpsw is restored. ov value read from ctpsw is restored. s value read from ctpsw is restored. z value read from ctpsw is restored. sat value read from ctpsw is restored. explanation fetches the restore pc and psw from the appropriate system register and returns from a routine called by callt instruct ion. the operations of this instruction are as follows: (1) the restore pc and psw are read from the ctpc and ctpsw. (2) once the pc and psw are restored to the retu rn values, control is transferred to the return address.
chapter 5 instruction 57 user?s manual u15943ej3v0um return from debug trap dbret return from debug trap instruction format dbret operation pc dbpc psw dbpsw format format x opcode 15 0 31 16 0000011111100000 0000000101000110 flag cy value read from dbpsw is restored. ov value read from dbpsw is restored. s value read from dbpsw is restored. z value read from dbpsw is restored. sat value read from dbpsw is restored. explanation fetches the restore pc and psw from the appropriate system register and returns from debug mode. caution because the dbret instruction is for debugging, it is essentially used by debug tools. when a debug tool is using this instruct ion, therefore, us e of it in the application may cause a malfunction.
chapter 5 instruction 58 user?s manual u15943ej3v0um debug trap dbtrap debug trap instruction format dbtrap operation dbpc pc + 2 (restore pc) dbpsw psw psw.np 1 psw.ep 1 psw.id 1 pc 00000060h format format i opcode 15 0 1111100001000000 flag cy ? ov ? s ? z ? sat ? explanation saves the contents of the re store pc (address of the in struction following the dbtrap instruction) and the psw to the dbpc and dbpsw , respectively, and sets the np, ep, and id flags of psw to 1. next, the handler address (00000060h) of the exception trap is set to the pc, and control shifts to the pc. psw flags other than np, ep, and id flags are unaffected. note that the value saved to the dbpc is the address of the instru ction following the dbtrap instruction. caution because the dbtrap instruction is for debugging, it is essentially us ed by debug tools. when a debug tool is using this instru ction, therefore, us e of it in the application may cause a malfunction.
chapter 5 instruction 59 user?s manual u15943ej3v0um disable interrupt di disable interrupt instruction format di operation psw.id 1 (disables maskable interrupt) format format x opcode 15 0 31 16 0000011111100000 0000000101100000 flag cy ? ov ? s ? z ? sat ? id 1 explanation sets the id flag of the psw to 1 to disabl e the acknowledgement of maskable interrupts during execution of this instruction. remark interrupts are not sampled during execution of th is instruction. the psw flag actually becomes valid at the start of the nex t instruction. but because in terrupts are not sampled during instruction execution, interrupt s are immediately disabled. n on-maskable interrupts (nmi) are not affected by this instruction.
chapter 5 instruction 60 user?s manual u15943ej3v0um function dispose dispose function dispose instruction format (1) dispose imm5, list12 (2) dispose imm5, list12, [reg1] operation (1) sp sp + zero-extend (imm5 logi cally shift left by 2) gr [reg in list12] load-memory (sp, word) sp sp + 4 repeat 2 steps above unt il all regs in list12 are loaded (2) sp sp + zero-extend (imm5 logi cally shift left by 2) gr [reg in list12] load-memory (sp, word) sp sp + 4 repeat 2 states above unt il all regs in list12 are loaded pc gr [reg1] format format xiii opcode 15 0 31 16 (1) 0000011001iiiiil lllllllllll00000 15 0 31 16 (2) 0000011001iiiiil lllllllllllrrrrr rrrrr must not be 00000. in addition, llllllllllll indicates the value of corresponding bit in the register list (list12) (for example, ?l? of the bit 21 in the opcode indicate s the value of bit 21 of the list12). the list12 is a 32-bit regist er list defined as follows. 31 30 29 28 27 26 25 24 23 22 21 20 ... 1 0 r24 r25 r26 r27 r20 r21 r22 r23 r28 r29 r31 ? r30 general-purpose registers (r20 to r31) co rrespond to the bits 31 to 21 and 0, and the register corresponding to the bit being set (to 1) is specified as the tar get of manipulation. any values can be set to bits 20 to 1 since these bits are not corresponding to registers.
chapter 5 instruction 61 user?s manual u15943ej3v0um flag cy ? ov ? s ? z ? sat ? explanation (1) adds the data of 5-bit immediate imm5, logically shifted left by 2 and zero-extended to word length, to sp. then pop (load data from t he address specified by sp and adds 4 to sp) general-purpose registers listed in list12. bit 0 of the address is masked to 0. (2) adds the data of 5-bit immediate imm5, logically shifted left by 2 and zero-extended to word length, to sp. then pop (load data from the address specified by sp and adds 4 to sp) general-purpose registers list ed in list12, transfers contro l to the address specified by general-purpose register reg1. bit 0 of the address is masked to 0. remark general-purpose registers in lis t12 are loaded in the downward di rection. (r31, r30, ... r20) the 5-bit immediate imm5 is used to restor e a stack frame for auto variables and temporary data. the lower 2-bit of address specified by sp is always masked to 0 even if misaligned access is enabled. if an interrupt occurs before updating the sp, execution is aborted, and the interrupt is processed. upon returning from the interrupt, the execution is restar ted from the beginning, with the return address being the start address of th is instruction (sp will retain their original values prior to the start of execution). caution if an interrupt is generated during instruction execution, due to m anipulation of the stack, the execution of that inst ruction may stop after the read/write cycle and register value rewriting are complete. execution is resumed a fter returning from the interrupt.
chapter 5 instruction 62 user?s manual u15943ej3v0um divide word div divide word instruction format div reg1, reg2, reg3 operation gr [reg2] gr [reg2] gr [reg1] gr [reg3] gr [reg2] % gr [reg1] format format xi opcode 15 0 31 16 rrrrr111111rrrrr wwwww01011000000 flag cy ? ov 1 if overflow occurs; otherwise, 0. s 1 if the operation result is negative; otherwise, 0. z 1 if the operation resu lt is 0; otherwise, 0. sat ? explanation divides the word data of gener al-purpose register reg2 by t he word data of general-purpose register reg1, and stores the quotient to general-purpose regist er reg2, and the remainder to general-purpose register reg3. if the data is divided by 0, overfl ow occurs, and the quotient is undefined. the data of general-purpose register reg1 is not affected. remark overflow occurs when the maximum negativ e value (80000000h) is divided by ?1 (in which case the quotient is 80000000h) and when data is di vided by 0 (in which case the quotient is undefined). if an interrupt occurs while this instruction is executed, execution is abor ted, and the interrupt is processed. upon returning from the interrupt, the execution is restar ted from the beginning, with the return address being the start address of this instruction. also, general-purpose registers reg1 and reg2 will retain their original values prior to the start of execution. if the address of reg2 is the same as the addr ess of reg3, the remai nder is stored in reg2 (= reg3).
chapter 5 instruction 63 user?s manual u15943ej3v0um divide halfword divh divide halfword instruction format (1) divh reg1, reg2 (2) divh reg1, reg2, reg3 operation (1) gr [reg2] gr [reg2] gr [reg1] (2) gr [reg2] gr [reg2] gr [reg1] gr [reg3] gr [reg2] % gr [reg1] format (1) format i (2) format xi opcode 15 0 (1) rrrrr000010rrrrr 15 0 31 16 (2) rrrrr111111rrrrr wwwww01010000000 flag cy ? ov 1 if overflow occurs; otherwise, 0. s 1 if the operation result is negative; otherwise, 0. z 1 if the operation resu lt is 0; otherwise, 0. sat ? explanation (1) divides the word data of general-purpose register reg2 by the lower halfword data of general-purpose register reg1, and stores the quot ient to general-purpose register reg2. if the data is divided by 0, overflow occurs , and the quotient is undef ined. the data of general-purpose register reg1 is not affected. (2) divides the word data of general-purpose register reg2 by the lower halfword data of general-purpose register reg1, and stores the quotient to gener al-purpose register reg2, the remainder to general-purpose register reg3. if the data is divided by 0, overflow occurs, and the quotient is undef ined. the data of general-pur pose register reg1 is not affected. remark (1) the remainder is not stored. over flow occurs when the maximum negative value (80000000h) is divided by ?1 (in which case the quotient is 80000000h) and when data is divided by 0 (in which case the quotient is undefined). if an interrupt occurs while this instruction is executed, exec ution is aborted, and the inte rrupt is processed. upon returning from the interrupt, the execution is restarted from the begi nning, with the return address being the start address of this instru ction. also, general-purpose registers reg1 and reg2 will retain their original values prior to the start of execution. do not specify r0 as t he destination register reg2. the higher 16 bits of general-purpose regist er reg1 are ignored when division is executed.
chapter 5 instruction 64 user?s manual u15943ej3v0um (2) overflow occurs when the maximum negative value (80000000h) is divided by ?1 (in which case the quotient is 80000000h) and when dat a is divided by 0 (in which case the quotient is undefined). if an interrupt occurs while this instruct ion is executed, execut ion is aborted, and the interrupt is processed. upon returning from the interrupt, the execut ion is restarted from the beginning, with the return address being the st art address of this instruction. also, general-purpose registers reg1 and r eg2 will retain their original values prior to the start of execution. the higher 16 bits of general-purpose regist er reg1 are ignored when division is executed. if the address of reg2 is the same as the addr ess of reg3, the remai nder is stored in reg2 (= reg3).
chapter 5 instruction 65 user?s manual u15943ej3v0um divide halfword unsigned divhu divide halfword unsigned instruction format divhu reg1, reg2, reg3 operation gr [reg2] gr [reg2] gr [reg1] gr [reg3] gr [reg2] % gr [reg1] format format xi opcode 15 0 31 16 rrrrr111111rrrrr wwwww01010000010 flag cy ? ov 1 if overflow occurs; otherwise, 0. s 1 if the operation result is negative; otherwise, 0. z 1 if the operation resu lt is 0; otherwise, 0. sat ? explanation divides the word data of gener al-purpose register reg2 by t he lower halfword data of general- purpose register reg1, and stor es the quotient to general-pur pose register reg2, and the remainder to general-purpose register reg3. if the data is divided by 0, overflow occurs, and the quotient is undefined. t he data of general-purpose regist er reg1 is not affected. remark overflow occurs when data is divided by 0 (in which case the quotient is undefined). if an interrupt occurs while this instruction is executed, execution is abor ted, and the interrupt is processed. upon returning from the interrupt, the execution is restar ted from the beginning, with the return address being the start address of this instruction. also, general-purpose registers reg1 and reg2 will retain their original values prior to the start of execution. if the address of reg2 is the same as the addr ess of reg3, the remai nder is stored in reg2 (= reg3).
chapter 5 instruction 66 user?s manual u15943ej3v0um divide word unsigned divu divide word unsigned instruction format divu reg1, reg2, reg3 operation gr [reg2] gr [reg2] gr [reg1] gr [reg3] gr [reg2] % gr [reg1] format format xi opcode 15 0 31 16 rrrrr111111rrrrr wwwww01011000010 flag cy ? ov 1 if overflow occurs; otherwise, 0. s 1 if the operation result is negative; otherwise, 0. z 1 if the operation resu lt is 0; otherwise, 0. sat ? explanation divides the word data of gener al-purpose register reg2 by t he word data of general-purpose register reg1, and stores the quotient to general-purpose regist er reg2, and the remainder to general-purpose register reg3. if the data is divided by 0, overfl ow occurs, and the quotient is undefined. the data of general-purpose register reg1 is not affected. remark overflow occurs when data is divided by 0 (in which case the quotient is undefined). if an interrupt occurs while this instruction is executed, execution is abor ted, and the interrupt is processed. upon returning from the interrupt, the execution is restar ted from the beginning, with the return address being the start address of this instruction. also, general-purpose registers reg1 and reg2 will retain their original values prior to the start of execution. if the address of reg2 is the same as the addr ess of reg3, the remai nder is stored in reg2 (= reg3).
chapter 5 instruction 67 user?s manual u15943ej3v0um enable interrupt ei enable interrupt instruction format ei operation psw.id 0 (enables maskable interrupt) format format x opcode 15 0 31 16 1000011111100000 0000000101100000 flag cy ? ov ? s ? z ? sat ? id 0 explanation clears the id flag of the psw to 0 and enables the acknowledgement of maskable interrupts beginning at the next instruction. remark interrupts are not sampled duri ng instruction execution.
chapter 5 instruction 68 user?s manual u15943ej3v0um halt halt halt instruction format halt operation halts format format x opcode 15 0 31 16 0000011111100000 0000000100100000 flag cy ? ov ? s ? z ? sat ? explanation stops the operating clock of the cpu and places the cpu in the halt mode. remark the halt mode is exited by any of the following three events: reset input non-maskable interrupt request (nmi input) unmasked maskable interrupt request (when id of psw = 0) if an interrupt is acknowledged during the halt mode, the address of t he following instruction is stored in eipc or fepc.
chapter 5 instruction 69 user?s manual u15943ej3v0um halfword swap word hsw halfword swap word instruction format hsw reg2, reg3 operation gr [reg3] gr [reg2] (15:0) || gr [reg2] (31:16) format format xii opcode 15 0 31 16 rrrrr11111100000 wwwww01101000100 flag cy 1 if one or more halfwords in result word is 0; otherwise 0. ov 0 s 1 if the msb of the word data of t he operation result is 1; otherwise, 0. z 1 if the word data of the operat ion result is 0; otherwise, 0. sat ? explanation endian translation.
chapter 5 instruction 70 user?s manual u15943ej3v0um jump and register link jarl jump and register link instruction format jarl disp22, reg2 operation gr [reg2] pc + 4 pc pc + sign-extend (disp22) format format v opcode 15 0 31 16 rrrrr11110dddddd ddddddddddddddd0 ddddddddddddddddddddd is the higher 21 bits of disp22. flag cy ? ov ? s ? z ? sat ? explanation saves the current pc value plus 4 to general- purpose register reg2, adds the current pc value and 22-bit displacement, sign-extended to word lengt h, and transfers control to that pc. bit 0 of the 22-bit displacement is masked to 0. remark the current pc value used for calc ulation is the address of the first byte of this instruction. if the displacement value is 0, the branch destination is this instruction itself. this instruction is equivalent to a call subrout ine instruction, and saves the restore pc address to general-purpose register reg2. the jmp instruction, which is equivalent to a subroutine- return instruction, can be used to specify as reg1 the general-purpose r egister containing the return address saved during the jarl subrouti ne-call instruction, to restore the program counter.
chapter 5 instruction 71 user?s manual u15943ej3v0um jump register jmp jump register instruction format jmp [reg1] operation pc gr [reg1] format format i opcode 15 0 00000000011rrrrr flag cy ? ov ? s ? z ? sat ? explanation transfers control to the address specified by general-purpose register reg1. bit 0 of the address is masked to 0. remark when using this instruction as the subroutine-return instruct ion, specify t he general-purpose register containing the return address saved dur ing the jarl subroutine- call instruction, to restore the program counter. w hen using the jarl instruction, which is equivalent to the subroutine-call instruction, st ore the pc return address in general-purpose register reg2.
chapter 5 instruction 72 user?s manual u15943ej3v0um jump relative jr jump relative instruction format jr disp22 operation pc pc + sign-extend (disp22) format format v opcode 15 0 31 16 0000011110dddddd ddddddddddddddd0 ddddddddddddddddddddd is the higher 21 bits of disp22. flag cy ? ov ? s ? z ? sat ? explanation adds the 22-bit displacement, sign-extended to wo rd length, to the curr ent pc value and stores the value in the pc, and then transfers control to that pc. bit 0 of the 22-bit displacement is masked to 0. remark the current pc value used for the calculation is the address of the first by te of this instruction itself. therefore, if the disp lacement value is 0, the jump destination is this instruction.
chapter 5 instruction 73 user?s manual u15943ej3v0um load byte ld.b load instruction format ld.b disp16 [reg1], reg2 operation adr gr [reg1] + sign-extend (disp16) gr [reg2] sign-extend (load-memory (adr, byte)) format format vii opcode 15 0 31 16 rrrrr111000rrrrr dddddddddddddddd flag cy ? ov ? s ? z ? sat ? explanation adds the data of general -purpose register reg1 to a 16-bit displacement sign-extended to word length to generate a 32-bit address. byte data is read from t he generated address, sign- extended to word length, and stored in general-purpose register reg2. remark if an interrupt occurs during instruction execut ion, execution is abort ed, and the interrupt is processed. upon returning from the interrupt, the execution is restar ted from the beginning, with the return address being the star t address of this instruction. depending on the resource to be accessed (inter nal rom, internal ram, on-chip peripheral i/o, external memory), the bus cycle may be switc hed (this will not occur if the same resource is accessed).
chapter 5 instruction 74 user?s manual u15943ej3v0um load byte unsigned ld.bu load instruction format ld.bu disp16 [reg1], reg2 operation adr gr [reg1] + sign-extend (disp16) gr [reg2] zero-extend (load-memory (adr, byte)) format format vii opcode 15 0 31 16 rrrrr11110brrrrr ddddddddddddddd1 ddddddddddddddd is the higher 15 bits of disp16. b is the bit 0 of disp16. flag cy ? ov ? s ? z ? sat ? explanation adds the data of general -purpose register reg1 to a 16-bit displacement sign-extended to word length to generate a 32-bit address. byte dat a is read from the generated address, zero- extended to word length, and stored in general-purpose register reg2. remark if an interrupt occurs during instruction execut ion, execution is abort ed, and the interrupt is processed. upon returning from the interrupt, the execution is restar ted from the beginning, with the return address being the star t address of this instruction. depending on the resource to be accessed (inter nal rom, internal ram, on-chip peripheral i/o, external memory), the bus cycle may be switc hed (this will not occur if the same resource is accessed).
chapter 5 instruction 75 user?s manual u15943ej3v0um load halfword ld.h load instruction format ld.h disp16 [reg1], reg2 operation adr gr [reg1] + sign-extend (disp16) gr [reg2] sign-extend (load-memory (adr, halfword)) format format vii opcode 15 0 31 16 rrrrr111001rrrrr ddddddddddddddd0 ddddddddddddddd is the higher 15 bits of disp16. flag cy ? ov ? s ? z ? sat ? explanation adds the data of general -purpose register reg1 to a 16-bit displacement sign-extended to word length to generate a 32-bit address. halfword data is read from t he generated address, sign- extended to word length, and stored in general-purpose register reg2. caution for notes on misaligned access occurrence, see 3.3 data alignment . remark if an interrupt occurs during instruction execut ion, execution is abort ed, and the interrupt is processed. upon returning from the interrupt, the execution is restar ted from the beginning, with the return address being the star t address of this instruction. depending on the resource to be accessed (inter nal rom, internal ram, on-chip peripheral i/o, external memory), the bus cycle may be switc hed (this will not occur if the same resource is accessed).
chapter 5 instruction 76 user?s manual u15943ej3v0um load halfword unsigned ld.hu load instruction format ld.hu disp16 [reg1], reg2 operation adr gr [reg1] + sign-extend (disp16) gr [reg2] zero-extend (load-memory (adr, halfword)) format format vii opcode 15 0 31 16 rrrrr111111rrrrr ddddddddddddddd1 ddddddddddddddd is the higher 15 bits of disp16. flag cy ? ov ? s ? z ? sat ? explanation adds the data of general -purpose register reg1 to a 16-bit displacement sign-extended to word length to generate a 32-bit address. halfword data is read from the generated address, zero- extended to word length, and stored in general-purpose register reg2. caution for notes on misaligned access occurrence, see 3.3 data alignment . remark if an interrupt occurs during instruction execut ion, execution is abort ed, and the interrupt is processed. upon returning from the interrupt, the execution is restar ted from the beginning, with the return address being the star t address of this instruction. depending on the resource to be accessed (inter nal rom, internal ram, on-chip peripheral i/o, external memory), the bus cycle may be switc hed (this will not occur if the same resource is accessed).
chapter 5 instruction 77 user?s manual u15943ej3v0um load word ld.w load instruction format ld.w disp16 [reg1], reg2 operation adr gr [reg1] + sign-extend (disp16) gr [reg2] load-memory (adr, word) format format vii opcode 15 0 31 16 rrrrr111001rrrrr ddddddddddddddd1 ddddddddddddddd is the higher 15 bits of disp16. flag cy ? ov ? s ? z ? sat ? explanation adds the data of general -purpose register reg1 to a 16-bit displacement sign-extended to word length to generate a 32-bit address. word data is read from the generated address. caution for notes on misaligned access occurrence, see 3.3 data alignment . remark if an interrupt occurs during instruction execut ion, execution is abort ed, and the interrupt is processed. upon returning from the interrupt, the execution is restar ted from the beginning, with the return address being the star t address of this instruction. depending on the resource to be accessed (inter nal rom, internal ram, on-chip peripheral i/o, external memory), the bus cycle may be switc hed (this will not occur if the same resource is accessed).
chapter 5 instruction 78 user?s manual u15943ej3v0um load to system register ldsr load to system register instruction format ldsr reg2, regid operation sr [regid] gr [reg2] format format ix opcode 15 0 31 16 rrrrr111111rrrrr 0000000000100000 caution the source register in this instruction is represented by reg2 for convenience of describing its mnemonic . in the opcode, however, the reg1 field is used for the source register. unlike other in structions therefore, the register specified in the mnemonic description has a different meaning in the opcode. rrrrr : regid specification rrrrr : reg2 specification flag cy ? (see remark below.) ov ? (see remark below.) s ? (see remark below.) z ? (see remark below.) sat ? (see remark below.) explanation loads the word data of general- purpose register reg2 to a system register specified by the system register number (regid). the data of general-purpose regi ster reg2 is not affected. remark if the system register number (regid) is equal to 5 (psw r egister), the values of the corresponding bits of the psw are set according to the contents of reg2. also, interrupts are not sampled when the psw is being written with a new value. if the id flag is enabled with this instruction, interrupt disabling begins at the start of executi on, even though the id flag does not become valid until the beginning of the next instruction. caution the system register number r egid is a number which identifie s a system register. accessing system registers which are rese rved or write-prohibited is prohibited and will lead to undefined results.
chapter 5 instruction 79 user?s manual u15943ej3v0um move register/immediate (5-bit)/immediate (32-bit) mov move instruction format (1) mov reg1, reg2 (2) mov imm5, reg2 (3) mov imm32, reg1 operation (1) gr [reg2] gr [reg1] (2) gr [reg2] sign-extend (imm5) (3) gr [reg1] imm32 format (1) format i (2) format ii (3) format vi opcode 15 0 (1) rrrrr000000rrrrr 15 0 (2) rrrrr010000iiiii 15 0 31 16 47 32 (3) 00000110001rrrrr iiiiiiiiiiiiiiii iiiiiiiiiiiiiiii i (bits 31 to 16) refers to the lowe r 16 bits of 32-bit immediate data. i (bits 47 to 32) refers to the higher 16 bits of 32-bit immediate data. flag cy ? ov ? s ? z ? sat ? explanation (1) transfers the word data of general-purpose r egister reg1 to general-pur pose register reg2. the data of general-pur pose register reg1 is not affected. (2) transfers the value of a 5-bit immediat e data, sign-extended to wo rd length, to general- purpose register reg2. do not specify r0 as t he destination register reg2. (3) transfers the value of a 32-bit imm ediate data to general-pur pose register reg1.
chapter 5 instruction 80 user?s manual u15943ej3v0um move effective address movea move effective address instruction format movea imm16, reg1, reg2 operation gr [reg2] gr [reg1] + sign-extend (imm16) format format vi opcode 15 0 31 16 rrrrr110001rrrrr iiiiiiiiiiiiiiii flag cy ? ov ? s ? z ? sat ? explanation adds the 16-bit immediate dat a, sign-extended to word length, to the word data of general- purpose register reg1, and stores the result to general-purpos e register reg2. the data of general-purpose register reg1 is not affected. the flags are not affected by the addition. do not specify r0 as t he destination register reg2. remark this instruction calculates a 32-bit address and stores the result wit hout affecting the psw flags.
chapter 5 instruction 81 user?s manual u15943ej3v0um move high halfword movhi move high halfword instruction format movhi imm16, reg1, reg2 operation gr [reg2] gr [reg1] + (imm16 ii 0 16 ) format format vi opcode 15 0 31 16 rrrrr110010rrrrr iiiiiiiiiiiiiiii flag cy ? ov ? s ? z ? sat ? explanation adds a word data, whose higher 16 bits are specified by the 16-bit immediate data and lower 16 bits are 0, to the word dat a of general-purpose regi ster reg1 and stores t he result in general- purpose register reg2. the data of general-purpose register reg1 is not affected. the flags are not affected by the addition. do not specify r0 as t he destination register reg2. remark this instruction is used to generate the higher 16 bits of a 32-bit address.
chapter 5 instruction 82 user?s manual u15943ej3v0um multiply word by register/immediate (9-bit) mul multiply word instruction format (1) mul reg1, reg2, reg3 (2) mul imm9, reg2, reg3 operation (1) gr [reg3] || gr [reg2] gr [reg2] gr [reg1] (2) gr [reg3] || gr [reg2] gr [reg2] sign-extend (imm9) format (1) format xi (2) format xii opcode 15 0 31 16 (1) rrrrr111111rrrrr wwwww01000100000 15 0 31 16 (2) rrrrr111111iiiii wwwww01001iiii00 iiiii is the lower 5 bits of 9-bit immediate data. iiii is the higher 4 bits of 9-bit immediate data. flag cy ? ov ? s ? z ? sat ? explanation (1) multiplies the word data of general-purpos e register reg2 by t he word data of general- purpose register reg1, and stores the higher 32 bits of the result (64-bit data) in general- purpose register reg3 and the lower 32 bits in general-purpose register reg2. the data of general-purpose register reg1 is not affected. (2) multiplies the word data of general-purpose register reg2 by a 9-bit immediate data, sign- extended to word length, and stores the higher 32 bits of the re sult (64-bit data) in general- purpose register reg3 and the lower 32 bi ts in general-purpose register reg2. remark if the address of reg2 is the same as the address of reg3, the higher 32 bi ts of the result are stored in reg2 (= reg3). caution in the ?mul reg1, reg2, reg3? in struction, do not use registers in combinations that satisfy all the following conditions; otherwise the operation is not guaranteed. ? reg1 = reg3 ? reg1 reg2 ? reg1 r0 ? reg3 r0
chapter 5 instruction 83 user?s manual u15943ej3v0um multiply halfword by register/immediate (5-bit) mulh multiply halfword instruction format (1) mulh reg1, reg2 (2) mulh imm5, reg2 operation (1) gr [reg2] (32) gr [reg2] (16) gr [reg1] (16) (2) gr [reg2] gr [reg2] sign-extend (imm5) format (1) format i (2) format ii opcode 15 0 (1) rrrrr000111rrrrr 15 0 (2) rrrrr010111iiiii flag cy ? ov ? s ? z ? sat ? explanation (1) multiplies the lower halfword data of general -purpose register reg2 by the halfword data of general-purpose register reg1, and stores the result to gener al-purpose register reg2 as word data. the data of general-purpose r egister reg1 is not affected. do not specify r0 as t he destination register reg2. (2) multiplies the lower halfword data of general -purpose register reg2 by a 5-bit immediate data, sign-extended to halfword length, and stores the result to general-purpose register reg2. do not specify r0 as t he destination register reg2. remark the higher 16 bits of general- purpose registers reg1 and reg2 ar e ignored in this operation.
chapter 5 instruction 84 user?s manual u15943ej3v0um multiply halfword by immediate (16-bit) mulhi multiply halfword immediate instruction format mulhi imm16, reg1, reg2 operation gr [reg2] gr [reg1] imm16 format format vi opcode 15 0 31 16 rrrrr110111rrrrr iiiiiiiiiiiiiiii flag cy ? ov ? s ? z ? sat ? explanation multiplies the lower halfword data of general- purpose register reg1 by the 16-bit immediate data, and stores the result to general-purpose register reg2. the data of general-purpose register reg1 is not affected. do not specify r0 as t he destination register reg2. remark the higher 16 bits of general-purpose regi ster reg1 are ignored in this operation.
chapter 5 instruction 85 user?s manual u15943ej3v0um multiply word by register/immediate (9-bit) mulu multiply word unsigned instruction format (1) mulu reg1, reg2, reg3 (2) mulu imm9, reg2, reg3 operation (1) gr [reg3] || gr [reg2] 15 0 31 16 (1) rrrrr111111rrrrr wwwww01000100010 15 0 31 16 (2) rrrrr111111iiiii wwwww01001iiii10 iiiii is the lower 5 bits of 9-bit immediate data. iiii is the higher 4 bits of 9-bit immediate data. flag cy ? ov ? s ? z ? sat ? explanation (1) multiplies the word data of general-purpos e register reg2 by t he word data of general- purpose register reg1, and stores the higher 32 bits of the result (64-bit data) in general- purpose register reg3 and the lower 32 bi ts in general-purpose register reg2. the data of general-purpose r egister reg1 is not affected. (2) multiplies the word data of general-purpose register reg2 by a 9-bit immediate data, zero- extended to word length, and stores the higher 32 bits of the re sult (64-bit data) in general- purpose register reg3 and the lower 32 bi ts in general-purpose register reg2. remark if the address of reg2 is the same as the address of reg3, the higher 32 bi ts of the result are stored in reg2 (= reg3). caution in the ?mulu reg1, reg2, reg3? in struction, do not use registers in combinations that satisfy all the following conditions; otherwise the operation is not guaranteed. ? ? ? ?
chapter 5 instruction 86 user?s manual u15943ej3v0um no operation nop no operation instruction format nop operation executes nothing and consum es at least one clock. format format i opcode 15 0 0000000000000000 flag cy ? ov ? s ? z ? sat ? explanation executes nothing and consumes at least one clock cycle. remark the contents of the pc are incr emented by two. the opcode is the same as that of mov r0, r0.
chapter 5 instruction 87 user?s manual u15943ej3v0um not not not instruction format not reg1, reg2 operation gr [reg2] not (gr [reg1]) format format i opcode 15 0 rrrrr000001rrrrr flag cy ? ov 0 s 1 if the msb of the word data of t he operation result is 1; otherwise, 0. z 1 if the operation resu lt is 0; otherwise, 0. sat ? explanation logically negates (takes the 1?s complement of) the word data of general-purpose register reg1, and stores the result to general -purpose register reg2. the data of general-pur pose register reg1 is not affected.
chapter 5 instruction 88 user?s manual u15943ej3v0um not bit not1 not bit instruction format (1) not1 bit#3, disp16 [reg1] (2) not1 reg2, [reg1] operation (1) adr gr [reg1] + sign-extend (disp16) z flag not (load-memory-bit (adr, bit#3)) store-memory-bit (adr, bit#3, z flag) (2) adr gr [reg1] z flag not (load-memory-bit (adr, reg2)) store-memory-bit (adr, reg2, z flag) format (1) format viii (2) format ix opcode 15 0 31 16 (1) 01bbb111110rrrrr dddddddddddddddd 15 0 31 16 (2) rrrrr111111rrrrr 0000000011100010 flag cy ? ov ? s ? z 1 if bit specified by operands = 0, 0 if bit specified by operands = 1 sat ? explanation (1) adds the data of general- purpose register reg1 to a 16-bi t displacement, sign-extended to word length to generate a 32-bit address. reads the byte data refe renced by the generated address, inverts the bit specifi ed by the 3-bit bit number (0 1 or 1 0), and rewrites the original address. (2) reads the data of general- purpose register reg1 to generat e a 32-bit address. reads the byte data referenced by the generated address, inverts the bi t specified by the data of lower 3 bits of reg2 (0 1 or 1 0), and rewrites the original address. remark the z flag of the psw indicates whether the spec ified bit was 0 or 1 before this instruction is executed, and does not indicate t he content of the spec ified bit after this instruction has been executed.
chapter 5 instruction 89 user?s manual u15943ej3v0um or or or instruction format or reg1, reg2 operation gr [reg2] gr [reg2] or gr [reg1] format format i opcode 15 0 rrrrr001000rrrrr flag cy ? ov 0 s 1 if the msb of the word data of the operation result is 1; otherwise, 0. z 1 if the operation resu lt is 0; otherwise, 0. sat ? explanation ors the word data of general-purpose regist er reg2 with the word data of general-purpose register reg1, and stores the result to general-purpose regist er reg2. the data of general- purpose register reg1 is not affected.
chapter 5 instruction 90 user?s manual u15943ej3v0um or immediate (16-bit) ori or immediate instruction format ori imm16, reg1, reg2 operation gr [reg2] gr [reg1] or zero-extend (imm16) format format vi opcode 15 0 31 16 rrrrr110100rrrrr iiiiiiiiiiiiiiii flag cy ? ov 0 s 1 if the msb of the word data of the operation result is 1; otherwise, 0. z 1 if the operation resu lt is 0; otherwise, 0. sat ? explanation ors the word data of general-pur pose register reg1 with the value of the 16-bit immediate data, zero-extended to word length, and stores the resu lt to general-purpose regi ster reg2. the data of general-purpose register reg1 is not affected.
chapter 5 instruction 91 user?s manual u15943ej3v0um function prepare prepare function prepare instruction format (1) prepare list12, imm5 (2) prepare list12, imm5, sp/imm note note sp/imm is specified by sub-opcode bits 20 and 19. operation (1) store-memory (sp ? 4, gr [reg in list12], word) sp sp ? 4 repeat 1 step above until a ll regs in list12 is stored sp sp ? zero-extend (imm5) (2) store-memory (sp ? 4, gr [reg in list12], word) sp sp ? 4 repeat 1 step above until a ll regs in list12 is stored sp sp ? zero-extend (imm5) ep sp/imm format format xiii opcode 15 0 31 16 (1) 0000011110iiiiil lllllllllll00001 15 0 31 16 optional(47 to 32 or 63 to 32) (2) 0000011110iiiiil lllllllllllff011 imm16 / imm32 in the case of 32-bit immediate data (imm32), bits 47 to 32 are the lower 16 bits of imm32, bits 63 to 48 are the higher 16 bits of imm32. ff = 00: load sp to ep ff = 01: load 16-bit immediate data (bits 47 to 32), sign-extended, to ep ff = 10: load 16-bit immediate data (bits 47 to 32), logically shifted left by 16, to ep ff = 11: load 32-bit immediate data (bits 63 to 32) to ep in addition, llllllllllll indicates the value of corresponding bit in the register list (list12) (for example, ?l? of the bit 21 in the opcode indicates the va lue of bit 21 of the list12). the list12 is a 32-bit regist er list defined as follows. 31 30 29 28 27 26 25 24 23 22 21 20 ... 1 0 r24 r25 r26 r27 r20 r21 r22 r23 r28 r29 r31 ? r30 general-purpose registers (r20 to r31) correspond to the bits 31 to 21 and 0, and the register corresponding to the bit being set (to 1) is specifi ed as the target of mani pulation. any values can be set to bits 20 to 1 since these bits are not corresponding to registers.
chapter 5 instruction 92 user?s manual u15943ej3v0um flag cy ? ov ? s ? z ? sat ? explanation (1) push (subtract 4 from sp and store the data to that address) general-purpose registers listed in list12. then s ubtract the data of 5-bi t immediate imm5, logically shifted left by 2 and zero-extended to word length, from sp. (2) push (subtract 4 from sp and store the data to that address) general-purpose registers listed in list12. then s ubtract the data of 5-bi t immediate imm5, logically shifted left by 2 and zero-extended to word length, from sp. next, load the data specifi ed by 3rd operand (sp/imm) to ep. remark general-purpose registers in list12 is stored on the upward di rection. (r20, r21, ... r31) the 5-bit immediate imm5 is used to make a stack frame for auto variables and temporary data. the lower 2 bits of the addr ess specified by sp are always masked to 0 even if misaligned access is enabled. if an interrupt occurs before updating the sp, execution is aborted, and the interrupt is processed. upon returning from the interrupt, the execution is restar ted from the beginning, with the return address being the start address of this instruction (sp and ep will retain their original values prior to the start of execution). caution if an interrupt is generated during instruction execution, due to m anipulation of the stack, the execution of that inst ruction may stop after the read/write cycle and register value rewriting are complete.
chapter 5 instruction 93 user?s manual u15943ej3v0um return from trap or interrupt reti return from trap or interrupt instruction format reti operation if psw.ep = 1 then pc eipc psw eipsw else if psw.np = 1 then pc fepc psw fepsw else pc eipc psw eipsw format format x opcode 15 0 31 16 0000011111100000 0000000101000000 flag cy value read from fepsw or eipsw is restored. ov value read from fepsw or eipsw is restored. s value read from fepsw or eipsw is restored. z value read from fepsw or eipsw is restored. sat value read from fepsw or eipsw is restored. explanation this instruction reads the restore pc and psw from the appropriate system register, and operation returns from a software exception or interrupt routine. t he operations of this instruction are as follows: (1) if the ep flag of the psw is 1, the re store pc and psw are read from the eipc and eipsw, regardless of the status of the np flag of the psw. if the ep flag of the psw is 0 and the np fl ag of the psw is 1, the restore pc and psw are read from the fepc and fepsw. if the ep flag of the psw is 0 and the np fl ag of the psw is 0, the restore pc and psw are read from the eipc and eipsw. (2) once the restore pc and psw values are set to the pc and psw, the operation returns to the address immediately before the trap or interrupt occurred.
chapter 5 instruction 94 user?s manual u15943ej3v0um caution when returning from a non-maskable interrupt or software exception routine using the reti instruction, the np and ep flags of psw must be set accordingly to restore the pc and psw: when returning from non-maskable interrupt routine using the reti instruction: np = 1 and ep = 0 when returning from a software excepti on routine using the re ti instruction: ep = 1 use the ldsr instruction for setting the flags. interrupts are not accepted in the latter half of the id stage during ldsr execution because of the operation of the in terrupt controller.
chapter 5 instruction 95 user?s manual u15943ej3v0um shift arithmetic right by register/immediate (5-bit) sar shift arithmetic right instruction format (1) sar reg1, reg2 (2) sar imm5, reg2 operation (1) gr [reg2] gr [reg2] arithmetically shift right by gr [reg1] (2) gr [reg2] gr [reg2] arithmetically shift right by zero-extend format (1) format ix (2) format ii opcode 15 0 31 16 (1) rrrrr111111rrrrr 0000000010100000 15 0 (2) rrrrr010101iiiii flag cy 1 if the bit shifted out last is 1; otherwise, 0. however, if the number of sh ifts is 0, the result is 0. ov 0 s 1 if the operation result is negative; otherwise, 0. z 1 if the operation resu lt is 0; otherwise, 0. sat ? explanation (1) arithmetically shifts the word data of general-purpose register r eg2 to the right by ?n? positions, where ?n? is a value from 0 to + 31, specified by the lo wer 5 bits of general- purpose register reg1 (after the shift, the msb pr ior to shift execution is copied and set as the new msb value), and then writes the result to general-purpose register reg2. if the number of shifts is 0, general -purpose register reg2 retains the same value prior to instruction execution. t he data of general-purpose regist er reg1 is not affected. (2) arithmetically shifts the word data of general-purpose register r eg2 to the right by ?n? positions, where ?n? is a value from 0 to +31, specified by the 5-bi t immediate data, zero- extended to word length (after the shift, the m sb prior to shift execution is copied and set as the new msb value), and then writes the result to general- purpose register reg2. if the number of shifts is 0, general -purpose register reg2 retains the same value prior to instruction execution.
chapter 5 instruction 96 user?s manual u15943ej3v0um shift and set flag condition sasf shift and set flag condition instruction format sasf cccc, reg2 operation if conditions are satisfied then gr [reg2] (gr [reg2] logically shift left by 1) or 00000001h else gr [reg2] (gr [reg2] logically shift left by 1) or 00000000h format format ix opcode 15 0 31 16 rrrrr1111110cccc 0000001000000000 flag cy ? ov ? s ? z ? sat ? explanation the general-purpose regist er reg2 is logically shifted left by 1, and its lsb is set to 1 if a condition specified by condition code ?cccc? is sa tisfied; otherwise, the general-purpose register reg2 is logically shifted left by 1, and its lsb is set to 0. one of the codes shown in table 5-5 condition codes should be specified as the condition code ?cccc?. remark see setf instruction.
chapter 5 instruction 97 user?s manual u15943ej3v0um saturated add register/immediate (5-bit) satadd saturated add instruction format (1) satadd reg1, reg2 (2) satadd imm5, reg2 operation (1) gr [reg2] saturated (gr [reg2] + gr [reg1]) (2) gr [reg2] saturated (gr [reg2] + sign-extend (imm5)) format (1) format i (2) format ii opcode 15 0 (1) rrrrr000110rrrrr 15 0 (2) rrrrr010001iiiii flag cy 1 if a carry occurs from msb; otherwise, 0. ov 1 if overflow occurs; otherwise, 0. s 1 if the result of the satura ted operation is negativ e; otherwise, 0. z 1 if the result of the satu rated operation is 0; otherwise, 0. sat 1 if ov = 1; otherwise, not affected. explanation (1) adds the word data of general-purpose register reg1 to the word data of general-purpose register reg2, and stores the resu lt to general-purpose register r eg2. however, if the result exceeds the maximum positiv e value 7fffffffh, 7fffffffh is stored in reg2; if the result exceeds the maximum negative va lue 80000000h, 80000000h is stored in reg2. the sat flag is set to 1. the data of gener al-purpose register r eg1 is not affected. do not specify r0 as t he destination register reg2. (2) adds a 5-bit immediate dat a, sign-extended to word length, to the word data of general- purpose register reg2, and stores the result to general-purpos e register reg2. however, if the result exceeds the maximum posit ive value 7fffffffh, 7fffffffh is stored in reg2; if the result exceeds the ma ximum negative value 80000000h, 80000000h is stored in reg2. the sat flag is set to 1. do not specify r0 as t he destination register reg2. remark the sat flag is a cumulative flag. once the result of the saturated operation instruction has been saturated, this flag is set to 1 and is not cleared to 0 even if the result of the subsequent operation is not saturated. even if the sat flag is set to 1, the satu rated operation instructi on is executed normally. caution to clear the sat flag to 0, load data to the psw by using the ldsr instruction.
chapter 5 instruction 98 user?s manual u15943ej3v0um saturated subtract satsub saturated subtract instruction format satsub reg1, reg2 operation gr [reg2] saturated (gr [reg2] ? gr [reg1]) format format i opcode 15 0 rrrrr000101rrrrr flag cy 1 if a borrow to msb occurs; otherwise, 0. ov 1 if overflow occurs; otherwise, 0. s 1 if the result of the saturat ed operation is negative; otherwise, 0. z 1 if the result of the satu rated operation is 0; otherwise, 0. sat 1 if ov = 1; otherwise, not affected. explanation subtracts the word data of general-purpose register reg1 fr om the word data of general- purpose register reg2, and stores the result to general-purpose register reg2. however, if the result exceeds the maximum positive value 7fffffffh, 7fffffffh is stored in reg2; if the result exceeds the maximum negative val ue 80000000h, 80000000h is stored in reg2. the sat flag is set to 1. the data of general -purpose register reg1 is not affected. do not specify r0 as t he destination register reg2. remark the sat flag is a cumulative flag. once the result of the operation of the saturated operation instruction has been saturated, this flag is set to 1 and is not cleared to 0 even if the result of the subsequent operations is not saturated. even if the sat flag is set to 1, the satu rated operation instructi on is executed normally. caution to clear the sat flag to 0, load data to the psw by using the ldsr instruction.
chapter 5 instruction 99 user?s manual u15943ej3v0um saturated subtract immediate satsubi saturated subtract immediate instruction format satsubi imm16, reg1, reg2 operation gr [reg2] saturated (gr [reg1] ? sign-extend (imm16)) format format vi opcode 15 0 31 16 rrrrr110011rrrrr iiiiiiiiiiiiiiii flag cy 1 if a borrow to msb occurs; otherwise, 0. ov 1 if overflow occurs; otherwise, 0. s 1 if the result of the satura ted operation is negativ e; otherwise, 0. z 1 if the result of the satu rated operation is 0; otherwise, 0. sat 1 if ov = 1; otherwise, not affected. explanation subtracts the 16-bit immediat e data, sign-extended to word l ength, from the word data of general-purpose register reg1, and stores the result to gener al-purpose register reg2. however, if the result exceeds the maxi mum positive value 7fffffffh, 7fffffffh is stored in reg2; if the result exceeds the ma ximum negative value 80000000h, 80000000h is stored in reg2. the sat flag is set to 1. the data of general-purpose register reg1 is not affected. do not specify r0 as t he destination register reg2. remark the sat flag is a cumulative flag. once the result of the operation of the saturated operation instruction has been saturated, this flag is set to 1 and is not cleared to 0 even if the result of the subsequent operations is not saturated. even if the sat flag is set to 1, the satu rated operation instructi on is executed normally. caution to clear the sat flag to 0, load data to the psw by using the ldsr instruction.
chapter 5 instruction 100 user?s manual u15943ej3v0um saturated subtract reverse satsubr saturated subtract reverse instruction format satsubr reg1, reg2 operation gr [reg2] saturated (gr [reg1] ? gr [reg2]) format format i opcode 15 0 rrrrr000100rrrrr flag cy 1 if a borrow to msb occurs; otherwise, 0. ov 1 if overflow occurs; otherwise, 0. s 1 if the result of the saturat ed operation is negative; otherwise, 0. z 1 if the result of the satu rated operation is 0; otherwise, 0. sat 1 if ov = 1; otherwise, not affected. explanation subtracts the word data of general-purpose register reg2 fr om the word data of general- purpose register reg1, and stores the result to general-purpose register reg2. however, if the result exceeds the maximum positive value 7fffffffh, 7fffffffh is stored in reg2; if the result exceeds the maximum negative val ue 80000000h, 80000000h is stored in reg2. the sat flag is set to 1. the data of general -purpose register reg1 is not affected. do not specify r0 as t he destination register reg2. remark the sat flag is a cumulative flag. once the result of the operation of the saturated operation instruction has been saturated, this flag is set to 1 and is not cleared to 0 even if the result of the subsequent operations is not saturated. even if the sat flag is set to 1, the satu rated operation instructi on is executed normally. caution to clear the sat flag to 0, load data to the psw by using the ldsr instruction.
chapter 5 instruction 101 user?s manual u15943ej3v0um set bit set1 set bit instruction format (1) set1 bit#3, disp16 [reg1] (2) set1 reg2, [reg1] operation (1) adr gr [reg1] + sign-extend (disp16) z flag not (load-memory-bit (adr, bit#3)) store-memory-bit (adr, bit#3, 1) (2) adr gr [reg1] z flag not (load-memory-bit (adr, reg2)) store-memory-bit (adr, reg2, 1) format (1) format viii (2) format ix opcode 15 0 31 16 (1) 00bbb111110rrrrr dddddddddddddddd 15 0 31 16 (2) rrrrr111111rrrrr 0000000011100000 flag cy ? ov ? s ? z 1 if bit specified by operands = 0, 0 if bit specified by operands = 1 sat ? explanation (1) adds the 16-bit displacement, sign-extended to word length, to t he data of general-purpose register reg1 to generate a 32-bit address. reads the byte data referenced by the generated address, sets the bit s pecified by the 3-bit bit num ber (to 1), and rewrites the original address. (2) reads the data of general- purpose register reg1 to generat e a 32-bit address. reads the byte data referenced by the generated address, sets the bit specified by the 3-bit bit number (to 1), and rewrites the original address. remark the z flag of the psw indicates whether the spec ified bit was 0 or 1 before this instruction is executed, and does not indicate t he content of the spec ified bit after this instruction has been executed.
chapter 5 instruction 102 user?s manual u15943ej3v0um set flag condition setf set flag condition instruction format setf cccc, reg2 operation if conditions are satisfied then gr [reg2] 00000001h else gr [reg2] 00000000h format format ix opcode 15 0 31 16 rrrrr1111110cccc 0000000000000000 flag cy ? ov ? s ? z ? sat ? explanation the general-purpose regist er reg2 is set to 1 if a condition specified by condition code ?cccc? is satisfied; otherwise, 0 are stored in the register. o ne of the codes shown in table 5-5 condition codes should be specified as the condition code ?cccc?. remark here are some examples of using this instruction: (1) translation of two or more condition clauses if a of statement if (a) in c language cons ists of two or more condition clauses (a 1 , a 2 , a 3 , and so on), it is usually trans lated to a sequence of if (a 1 ) then, if (a 2 ) then. the object code executes ?conditional branch? by checking t he result of evaluation equivalent to a n . since a pipeline processor takes more time to ex ecute ?condition judgment? + ?branch? than to execute an ordinary operation, the result of evaluati ng each condition clause if (a n ) is stored in register ra. by per forming a logical operation to ra n after all the condition clauses have been evaluated, the delay due to the pipeline can be prevented. (2) double-length operation to execute a double-length operat ion such as add with carry, t he result of the cy flag can be stored in general-purpose regist er reg2. therefore, a carry from the lower bits can be expressed as a numeric value.
chapter 5 instruction 103 user?s manual u15943ej3v0um table 5-5. condition codes condition code (cccc) condition name condition expression 0000 v ov = 1 1000 nv ov = 0 0001 c/l cy = 1 1001 nc/nl cy = 0 0010 z z = 1 1010 nz z = 0 0011 nh (cy or z) = 1 1011 h (cy or z) = 0 0100 s/n s = 1 1100 ns/p s = 0 0101 t always (unconditional) 1101 sa sat = 1 0110 lt (s xor ov) = 1 1110 ge (s xor ov) = 0 0111 le ((s xor ov) or z) = 1 1111 gt ((s xor ov) or z) = 0
chapter 5 instruction 104 user?s manual u15943ej3v0um shift logical left by register/immediate (5-bit) shl shift logical left instruction format (1) shl reg1, reg2 (2) shl imm5, reg2 operation (1) gr [reg2] gr [reg2] logically shift left by gr [reg1] (2) gr [reg2] gr [reg2] logically shi ft left by zero-extend (imm5) format (1) format ix (2) format ii opcode 15 0 31 16 (1) rrrrr111111rrrrr 0000000011000000 15 0 (2) rrrrr010110iiiii flag cy 1 if the bit shifted out last is 1; otherwise, 0. however, if the number of sh ifts is 0, the result is 0. ov 0 s 1 if the operation result is negative; otherwise, 0. z 1 if the operation resu lt is 0; otherwise, 0. sat ? explanation (1) logically shifts the word data of general-pur pose register reg2 to the left by ?n? positions, where ?n? is a value from 0 to +31, specified by the lower 5 bits of general-purpose register reg1 (0 is shifted to the lsb side), and then wr ites the result to general-purpose register reg2. if the number of shifts is 0, general- purpose register reg2 retains the same value prior to instruction execution. the data of general-purpose r egister reg1 is not affected. (2) logically shifts the word data of general-pur pose register reg2 to the left by ?n? positions, where ?n? is a value from 0 to +31, specifi ed by the 5-bit immediat e data, zero-extended to word length (0 is shifted to the lsb side) , and then writes the re sult to general-purpose register reg2. if the number of shifts is 0, general-purpose register reg2 retains the value prior to instruction execution.
chapter 5 instruction 105 user?s manual u15943ej3v0um shift logical right by register/immediate (5-bit) shr shift logical right instruction format (1) shr reg1, reg2 (2) shr imm5, reg2 operation (1) gr [reg2] gr [reg2] logically shift right by gr [reg1] (2) gr [reg2] gr [reg2] logically shift right by zero-extend (imm5) format (1) format ix (2) format ii opcode 15 0 31 16 (1) rrrrr111111rrrrr 0000000010000000 15 0 (2) rrrrr010100iiiii flag cy 1 if the bit shifted out last is 1; otherwise, 0. however, if the number of sh ifts is 0, the result is 0. ov 0 s 1 if the operation result is negative; otherwise, 0. z 1 if the operation resu lt is 0; otherwise, 0. sat ? explanation (1) logically shifts the word data of general-purpos e register reg2 to the right by ?n? positions where ?n? is a value from 0 to +31, specified by the lower 5 bits of general-purpose register reg1 (0 is shifted to the msb side). this instruction then writes the result to general- purpose register reg2. if the number of shifts is 0, general-purpose register reg2 retains the same value prior to instruction execution. the data of general-pur pose register reg1 is not affected. (2) logically shifts the word data of general-purpos e register reg2 to the right by ?n? positions, where ?n? is a value from 0 to +31, specifi ed by the 5-bit immediat e data, zero-extended to word length (0 is shifted to the msb side). this instruction then wr ites the result to general-purpose register reg2. if the number of shifts is 0, general-purpose register reg2 retains the same value prior to instruction execution.
chapter 5 instruction 106 user?s manual u15943ej3v0um short format load byte sld.b load instruction format sld.b disp7 [ep], reg2 operation adr ep + zero-extend (disp7) gr [reg2] sign-extend (load-memory (adr, byte)) format format iv opcode 15 0 rrrrr0110ddddddd flag cy ? ov ? s ? z ? sat ? explanation adds the 7-bit displacement, zero-extended to wo rd length, to the elem ent pointer to generate a 32-bit address. byte data is read from t he generated address, sign-ex tended to word length, and stored in reg2. remark if an interrupt occurs during instruction execut ion, execution is abort ed, and the interrupt is processed. upon returning from the interrupt, the execution is restar ted from the beginning, with the return address being the star t address of this instruction. depending on the resource to be accessed (inter nal rom, internal ram, on-chip peripheral i/o, external memory), the bus cycle may be switc hed (this will not occur if the same resource is accessed). caution (1) if an interrupt is generated during instruction execution, the executi on of that instruction may stop after the end of the read/ write cycle. in this case, t he instruction is re-executed after returning from the interrupt. therefore, except in cases when clearly no interrupt is generated, the ld instructi on should be used for accessing i/o, fifo types, or other resources whose status is changed by the read cycle (the bus cycle is not re-executed even if an interrupt is generated while the ld or store instruction is being executed). (2) for the restriction on the conflict between t he sld instruction and an interrupt request, refer to appendix a notes .
chapter 5 instruction 107 user?s manual u15943ej3v0um short format load byte unsigned sld.bu load instruction format sld.bu disp4 [ep], reg2 operation adr ep + zero-extend (disp4) gr [reg2] zero-extend (load-memory (adr, byte)) format format iv opcode 15 0 rrrrr0000110dddd rrrrr must not be 00000. flag cy ? ov ? s ? z ? sat ? explanation adds the 4-bit displacement, zero-extended to wo rd length, to the elem ent pointer to generate a 32-bit address. byte data is read from t he generated address, zero-e xtended to word length, and stored in reg2. remark if an interrupt occurs during instruction execut ion, execution is abort ed, and the interrupt is processed. upon returning from the interrupt, the execution is restar ted from the beginning, with the return address being the star t address of this instruction. depending on the resource to be accessed (inter nal rom, internal ram, on-chip peripheral i/o, external memory), the bus cycle may be switc hed (this will not occur if the same resource is accessed). caution (1) if an interrupt is generated during instruction execution, the executi on of that instruction may stop after the end of the read/ write cycle. in this case, t he instruction is re-executed after returning from the interrupt. therefore, except in cases when clearly no interrupt is generated, the ld instructi on should be used for accessing i/o, fifo types, or other resources whose status is changed by the read cycle (the bus cycle is not re-executed even if an interrupt is generated while the ld or store instruction is being executed). (2) for the restriction on the conflict between t he sld instruction and an interrupt request, refer to appendix a notes .
chapter 5 instruction 108 user?s manual u15943ej3v0um short format load halfword sld.h load instruction format sld.h disp8 [ep], reg2 operation adr ep + zero-extend (disp8) gr [reg2] sign-extend (load-memory (adr, halfword)) format format iv opcode 15 0 rrrrr1000ddddddd ddddddd is the higher 7 bits of disp8. flag cy ? ov ? s ? z ? sat ? explanation adds the 8-bit displacement, zero-extended to wo rd length, to the elem ent pointer to generate a 32-bit address. halfword data is read fr om the generated address, sign-extended to word length, and stored in reg2. remark if an interrupt occurs during instruction execut ion, execution is abort ed, and the interrupt is processed. upon returning from the interrupt, the execution is restar ted from the beginning, with the return address being the star t address of this instruction. depending on the resource to be accessed (inter nal rom, internal ram, on-chip peripheral i/o, external memory), the bus cycle may be switc hed (this will not occur if the same resource is accessed). caution (1) for notes on misaligned access occurrence, see 3.3 data alignment . also, if an interrupt is generated during inst ruction execution, t he execution of that instruction may stop after the end of the read/write cycle. in this case, the instruction is re- executed after returning from the interrupt. therefore, except in cases when clearly no interrupt is generated, the ld instruction should be used for accessing i/o, fifo types, or other resources whose stat us is changed by the read cycl e (the bus cycle is not re- executed even if an interrupt is generated while the ld or store instruction is being executed). (2) for the restriction on the conflict between t he sld instruction and an interrupt request, refer to appendix a notes .
chapter 5 instruction 109 user?s manual u15943ej3v0um short format load halfword unsigned sld.hu load instruction format sld.hu disp5 [ep], reg2 operation adr ep + zero-extend (disp5) gr [reg2] zero-extend (load-memory (adr, halfword)) format format iv opcode 15 0 rrrrr0000111dddd dddd is the higher 4 bits of disp5. rrrrr must not be 00000. flag cy ? ov ? s ? z ? sat ? explanation adds the 5-bit displacement, zero-extended to wo rd length, to the elem ent pointer to generate a 32-bit address. halfword data is read fr om the generated address, zero-extended to word length, and stored in reg2. remark if an interrupt occurs during instruction execut ion, execution is abort ed, and the interrupt is processed. upon returning from the interrupt, the execution is restar ted from the beginning, with the return address being the star t address of this instruction. depending on the resource to be accessed (inter nal rom, internal ram, on-chip peripheral i/o, external memory), the bus cycle may be switc hed (this will not occur if the same resource is accessed). caution (1) for notes on misaligned access occurrence, see 3.3 data alignment . also, if an interrupt is generated during inst ruction execution, t he execution of that instruction may stop after the end of the read/write cycle. in this case, the instruction is re- executed after returning from the interrupt. therefore, except in cases when clearly no interrupt is generated, the ld instruction should be used for accessing i/o, fifo types, or other resources whose stat us is changed by the read cycl e (the bus cycle is not re- executed even if an interrupt is generated while the ld or store instruction is being executed). (2) for the restriction on the conflict between t he sld instruction and an interrupt request, refer to appendix a notes .
chapter 5 instruction 110 user?s manual u15943ej3v0um short format load word sld.w load instruction format sld.w disp8 [ep], reg2 operation adr ep + zero-extend (disp8) gr [reg2] load-memory (adr, word) format format iv opcode 15 0 rrrrr1010dddddd0 dddddd is the higher 6 bits of disp8. flag cy ? ov ? s ? z ? sat ? explanation adds the 8-bit displacement, zero-extended to wo rd length, to the elem ent pointer to generate a 32-bit address. word data is read from the generated address, and stored in reg2. remark if an interrupt occurs during instruction execut ion, execution is abort ed, and the interrupt is processed. upon returning from the interrupt, the execution is restar ted from the beginning, with the return address being the star t address of this instruction. depending on the resource to be accessed (inter nal rom, internal ram, on-chip peripheral i/o, external memory), the bus cycle may be switc hed (this will not occur if the same resource is accessed). caution (1) for notes on misaligned access occurrence, see 3.3 data alignment . also, if an interrupt is generated during inst ruction execution, t he execution of that instruction may stop after the end of the read/write cycle. in this case, the instruction is re- executed after returning from the interrupt. therefore, except in cases when clearly no interrupt is generated, the ld instruction should be used for accessing i/o, fifo types, or other resources whose stat us is changed by the read cycl e (the bus cycle is not re- executed even if an interrupt is generated while the ld or store instruction is being executed). (2) for the restriction on the conflict between t he sld instruction and an interrupt request, refer to appendix a notes .
chapter 5 instruction 111 user?s manual u15943ej3v0um short format store byte sst.b store instruction format sst.b reg2, disp7 [ep] operation adr ep + zero-extend (disp7) store-memory (adr, gr [reg2], byte) format format iv opcode 15 0 rrrrr0111ddddddd flag cy ? ov ? s ? z ? sat ? explanation adds the 7-bit displacement, zero-extended to wo rd length, to the elem ent pointer to generate a 32-bit address, and stores the data of the lowest byte of reg2 in the generated address. remark if an interrupt occurs during instruction execut ion, execution is abort ed, and the interrupt is processed. upon returning from the interrupt, the execution is restar ted from the beginning, with the return address being the star t address of this instruction. depending on the resource to be accessed (inter nal rom, internal ram, on-chip peripheral i/o, external memory), the bus cycle may be switc hed (this will not occur if the same resource is accessed).
chapter 5 instruction 112 user?s manual u15943ej3v0um short format store halfword sst.h store instruction format sst.h reg2, disp8 [ep] operation adr ep + zero-extend (disp8) store-memory (adr, gr [reg2], halfword) format format iv opcode 15 0 rrrrr1001ddddddd ddddddd is the higher 7 bits of disp8. flag cy ? ov ? s ? z ? sat ? explanation adds the 8-bit displacement, zero-extended to wo rd length, to the elem ent pointer to generate a 32-bit address, and stores the lower halfw ord data of reg2 in the generated address. caution for notes on misaligned access occurrence, see 3.3 data alignment . remark if an interrupt occurs during instruction execut ion, execution is abort ed, and the interrupt is processed. upon returning from the interrupt, the execution is restar ted from the beginning, with the return address being the star t address of this instruction. depending on the resource to be accessed (inter nal rom, internal ram, on-chip peripheral i/o, external memory), the bus cycle may be switc hed (this will not occur if the same resource is accessed).
chapter 5 instruction 113 user?s manual u15943ej3v0um short format store word sst.w store instruction format sst.w reg2, disp8 [ep] operation adr ep + zero-extend (disp8) store-memory (adr, gr [reg2], word) format format iv opcode 15 0 rrrrr1010dddddd1 dddddd is the higher 6 bits of disp8. flag cy ? ov ? s ? z ? sat ? explanation adds the 8-bit displacement, zero-extended to wo rd length, to the elem ent pointer to generate a 32-bit address, and stores the word data of reg2 in t he generated address. caution for notes on misaligned access occurrence, see 3.3 data alignment . remark if an interrupt occurs during instruction execut ion, execution is abort ed, and the interrupt is processed. upon returning from the interrupt, the execution is restar ted from the beginning, with the return address being the star t address of this instruction. depending on the resource to be accessed (inter nal rom, internal ram, on-chip peripheral i/o, external memory), the bus cycle may be switc hed (this will not occur if the same resource is accessed).
chapter 5 instruction 114 user?s manual u15943ej3v0um store byte st.b store instruction format st.b reg2, disp16 [reg1] operation adr gr [reg1] + sign-extend (disp16) store-memory (adr, gr [reg2], byte) format format vii opcode 15 0 31 16 rrrrr111010rrrrr dddddddddddddddd flag cy ? ov ? s ? z ? sat ? explanation adds the 16-bit displacement, sign-extended to word length, to t he data of general-purpose register reg1 to generate a 32-bi t address, and stores the lowest byte data of general-purpose register reg2 to the generated address. remark if an interrupt occurs during instruction execut ion, execution is abort ed, and the interrupt is processed. upon returning from the interrupt, the execution is restar ted from the beginning, with the return address being the star t address of this instruction. depending on the resource to be accessed (inter nal rom, internal ram, on-chip peripheral i/o, external memory), the bus cycle may be switc hed (this will not occur if the same resource is accessed).
chapter 5 instruction 115 user?s manual u15943ej3v0um store halfword st.h store instruction format st.h reg2, disp16 [reg1] operation adr gr [reg1] + sign-extend (disp16) store-memory (adr, gr [reg2], halfword) format format vii opcode 15 0 31 16 rrrrr111011rrrrr ddddddddddddddd0 ddddddddddddddd is the higher 15 bits of disp16. flag cy ? ov ? s ? z ? sat ? explanation adds the 16-bit displacement, sign-extended to word length, to t he data of general-purpose register reg1 to generate a 32- bit address, and stores the lo wer halfword data of general- purpose register reg2 in the generated address. caution for notes on misaligned access occurrence, see 3.3 data alignment . remark if an interrupt occurs during instruction execut ion, execution is abort ed, and the interrupt is processed. upon returning from the interrupt, the execution is restar ted from the beginning, with the return address being the star t address of this instruction. depending on the resource to be accessed (inter nal rom, internal ram, on-chip peripheral i/o, external memory), the bus cycle may be switc hed (this will not occur if the same resource is accessed).
chapter 5 instruction 116 user?s manual u15943ej3v0um store word st.w store instruction format st.w reg2, disp16 [reg1] operation adr gr [reg1] + sign-extend (disp16) store-memory (adr, gr [reg2], word) format format vii opcode 15 0 31 16 rrrrr111011rrrrr ddddddddddddddd1 ddddddddddddddd is the higher 15 bits of disp16. flag cy ? ov ? s ? z ? sat ? explanation adds the 16-bit displacement, sign-extended to word length, to t he data of general-purpose register reg1 to generate a 32-bit address, and stores the word data of general-purpose register reg2 in the generated address. caution for notes on misaligned access occurrence, see 3.3 data alignment . remark if an interrupt occurs during instruction execut ion, execution is abort ed, and the interrupt is processed. upon returning from the interrupt, the execution is restar ted from the beginning, with the return address being the star t address of this instruction. depending on the resource to be accessed (inter nal rom, internal ram, on-chip peripheral i/o, external memory), the bus cycle may be switc hed (this will not occur if the same resource is accessed).
chapter 5 instruction 117 user?s manual u15943ej3v0um store contents of system register stsr store contents of system register instruction format stsr regid, reg2 operation gr [reg2] sr [regid] format format ix opcode 15 0 31 16 rrrrr111111rrrrr 0000000001000000 flag cy ? ov ? s ? z ? sat ? explanation stores the contents of a system register specified by system register number (regid) to general-purpose register reg2. the contents of the system register are not affected. caution the system register number regi d is a number which identifies a system register. accessing a system register which is reserved is prohibited and will lead to undefined results.
chapter 5 instruction 118 user?s manual u15943ej3v0um subtract sub subtract instruction format sub reg1, reg2 operation gr [reg2] gr [reg2] ? gr [reg1] format format i opcode 15 0 rrrrr001101rrrrr flag cy 1 if a borrow to msb occurs; otherwise, 0. ov 1 if overflow occurs; otherwise, 0. s 1 if the operation result is negative; otherwise, 0. z 1 if the operation resu lt is 0; otherwise, 0. sat ? explanation subtracts the word data of general-purpose register reg1 fr om the word data of general- purpose register reg2, and stores the result to general-purpos e register reg2. the data of general-purpose register reg1 is not affected.
chapter 5 instruction 119 user?s manual u15943ej3v0um subtract reverse subr subtract reverse instruction format subr reg1, reg2 operation gr [reg2] gr [reg1] ? gr [reg2] format format i opcode 15 0 rrrrr001100rrrrr flag cy 1 if a borrow to msb occurs; otherwise, 0. ov 1 if overflow occurs; otherwise, 0. s 1 if the operation result is negative; otherwise, 0. z 1 if the operation resu lt is 0; otherwise, 0. sat ? explanation subtracts the word data of general-purpose register reg2 fr om the word data of general- purpose register reg1, and stores the result to general-purpos e register reg2. the data of general-purpose register reg1 is not affected.
chapter 5 instruction 120 user?s manual u15943ej3v0um jump with table look up switch jump with table look up instruction format switch reg1 operation adr (pc + 2) + (gr [reg1] logically shift left by 1) pc ( pc + 2) + (sign-extend (load-memory (adr , halfword))) logically shift left by 1 format format i opcode 15 0 00000000010rrrrr flag cy ? ov ? s ? z ? sat ? explanation <1> adds the table entry address (address following switch instruction) and data of general-purpose register reg1 logically shift ed left by 1, and generates 32-bit table entry address. <2> loads halfword data pointed by address generated in <1>. <3> sign-extends the loaded halfword data to word length, and adds t he table entry address after logically shifts it left by 1 bit ( next address following switch instruction) to generate a 32-bit target address. <4> then jumps to the target address generated in <3>.
chapter 5 instruction 121 user?s manual u15943ej3v0um sign extend byte sxb sign extend byte instruction format sxb reg1 operation gr [reg1] sign-extend (gr [reg1] (7:0)) format format i opcode 15 0 00000000101rrrrr flag cy ? ov ? s ? z ? sat ? explanation sign-extends the lowest byte of general -purpose register reg1 to word length.
chapter 5 instruction 122 user?s manual u15943ej3v0um sign extend halfword sxh sign extend halfword instruction format sxh reg1 operation gr [reg1] sign-extend (gr [reg1] (15:0)) format format i opcode 15 0 00000000111rrrrr flag cy ? ov ? s ? z ? sat ? explanation sign-extends the lower halfword of general -purpose register reg1 to word length.
chapter 5 instruction 123 user?s manual u15943ej3v0um trap trap trap instruction format trap vector operation eipc pc + 4 (restore pc) eipsw psw ecr.eicc interrupt code psw.ep 1 psw.id 1 pc 00000040h (vector = 00h to 0fh) 00000050h (vector = 10h to 1fh) format format x opcode 15 0 31 16 00000111111iiiii 0000000100000000 flag cy ? ov ? s ? z ? sat ? explanation saves the restore pc and psw to eipc and ei psw, respectively; sets the exception code (eicc of ecr) and the flags of the psw (sets ep and id flags to 1); jumps to the handler address corresponding to the trap vector (00h to 1f h) specified by vector , and starts exception processing. the flags of psw other than ep and id flags are not affected. the restore pc is the address of the in struction following the trap instruction.
chapter 5 instruction 124 user?s manual u15943ej3v0um test tst test instruction format tst reg1, reg2 operation result gr [reg2] and gr [reg1] format format i opcode 15 0 rrrrr001011rrrrr flag cy ? ov 0 s 1 if the operation result is negative; otherwise, 0. z 1 if the operation resu lt is 0; otherwise, 0. sat ? explanation ands the word data of general -purpose register reg2 with t he word data of general-purpose register reg1. the result is not stored, and only the flags are changed. the data of general- purpose registers reg1 and reg2 are not affected.
chapter 5 instruction 125 user?s manual u15943ej3v0um test bit tst1 test bit instruction format (1) tst1 bit#3, disp16 [reg1] (2) tst1 reg2, [reg1] operation (1) adr gr [reg1] + sign-extend (disp16) z flag not (load-memory-bit (adr, bit#3)) (2) adr gr [reg1] z flag not (load-memory-bit (adr, reg2)) format (1) format viii (2) format ix opcode 15 0 31 16 (1) 11bbb111110rrrrr dddddddddddddddd 15 0 31 16 (2) rrrrr111111rrrrr 0000000011100110 flag cy ? ov ? s ? z 1 if bit specified by operands = 0, 0 if bit specified by operands = 1 sat ? explanation (1) adds the data of general- purpose register reg1 to a 16-bi t displacement, sign-extended to word length, to generate a 32-bit address. perf orms the test on the bi t, specified by the 3- bit bit number, at the byte data location referenced by the gener ated address. if the specified bit is 0, the z flag of psw is set to 1; if the bit is 1, the z fl ag is cleared to 0. the byte data, including the spec ified bit, is not affected. (2) reads the data of general- purpose register reg1 to generat e a 32-bit address. performs the test on the bit, specified by the lower 3-bits of reg2, at the byte data location referenced by the generated address. if the spec ified bit is 0, the z flag of psw is set to 1; if the bit is 1, the z flag is cleared to 0. the byte data, including the specified bit, is not affected.
chapter 5 instruction 126 user?s manual u15943ej3v0um exclusive or xor exclusive or instruction format xor reg1, reg2 operation gr [reg2] gr [reg2] xor gr [reg1] format format i opcode 15 0 rrrrr001001rrrrr flag cy ? ov 0 s 1 if the operation result is negative; otherwise, 0. z 1 if the operation re sult is 0; otherwise, 0. sat ? explanation exclusively ors the word data of general-purpos e register reg2 with t he word data of general- purpose register reg1, and stores the result to general-purpos e register reg2. the data of general-purpose register reg1 is not affected.
chapter 5 instruction 127 user?s manual u15943ej3v0um exclusive or immediate (16-bit) xori exclusive or immediate instruction format xori imm16, reg1, reg2 operation gr [reg2] gr [reg1] xor zero-extend (imm16) format format vi opcode 15 0 31 16 rrrrr110101rrrrr iiiiiiiiiiiiiiii flag cy ? ov 0 s 1 if the operation result is negative; otherwise, 0. z 1 if the operation resu lt is 0; otherwise, 0. sat ? explanation exclusively ors the word data of general-purpos e register reg1 with a 16-bit immediate data, zero-extended to word length, and stores the resu lt to general-purpose regi ster reg2. the data of general-purpose register reg1 is not affected.
chapter 5 instruction 128 user?s manual u15943ej3v0um zero extend byte zxb zero extend byte instruction format zxb reg1 operation gr [reg1] zero-extend (gr [reg1] (7:0)) format format i opcode 15 0 00000000100rrrrr flag cy ? ov ? s ? z ? sat ? explanation zero-extends the lowest byte of general -purpose register reg1 to word length.
chapter 5 instruction 129 user?s manual u15943ej3v0um zero extend halfword zxh zero extend halfword instruction format zxh reg1 operation gr [reg1] zero-extend (gr [reg1] (15:0)) format format i opcode 15 0 00000000110rrrrr flag cy ? ov ? s ? z ? sat ? explanation zero-extends the lower halfword of general -purpose register reg1 to word length.
chapter 5 instruction 130 user?s manual u15943ej3v0um 5.4 number of instruction execution clock cycles a list of the number of instru ction execution clocks when the internal rom or internal ram is used is shown below. the number of instruction ex ecution clock cycles differ depending on the combi nation of instructions. for details, see chapter 8 pipeline . table 5-6. list of number of in struction execution clock cycles (1/3) number of execution clocks type of instruction mnemonic operand byte i r l ld.b disp16 [reg1] , reg2 4 1 1 note 1 ld.h disp16 [reg1] , reg2 4 1 1 note 1 ld.w disp16 [reg1] , reg2 4 1 1 note 1 ld.bu disp16 [reg1] , reg2 4 1 1 note 1 ld.hu disp16 [reg1] , reg2 4 1 1 note 1 sld.b disp7 [ep] , reg2 2 1 1 note 2 sld.bu disp4 [ep] , reg2 2 1 1 note 2 sld.h disp8 [ep] , reg2 2 1 1 note 2 sld.hu disp5 [ep] , reg2 2 1 1 note 2 load instructions sld.w disp8 [ep] , reg2 2 1 1 note 2 st.b reg2, disp16 [reg1] 4 1 1 1 st.h reg2, disp16 [reg1] 4 1 1 1 st.w reg2, disp16 [reg1] 4 1 1 1 sst.b reg2, disp7 [ep] 2 1 1 1 sst.h reg2, disp8 [ep] 2 1 1 1 store instructions sst.w reg2, disp8 [ep] 2 1 1 1 mul reg1, reg2, reg3 4 1 4 5 mul imm9, reg2, reg3 4 1 4 5 mulh reg1, reg2 2 1 1 2 mulh imm5, reg2 2 1 1 2 mulhi imm16, reg1, reg2 4 1 1 2 mulu reg1, reg2, reg3 4 1 4 5 multiply instructions mulu imm9, reg2, reg3 4 1 4 5 add reg1, reg2 2 1 1 1 add imm5, reg2 2 1 1 1 addi imm16, reg1, reg2 4 1 1 1 cmov cccc, reg1, reg2, reg3 4 1 1 1 cmov cccc, imm5, reg2, reg3 4 1 1 1 cmp reg1, reg2 2 1 1 1 cmp imm5, reg2 2 1 1 1 div reg1, reg2, reg3 4 35 35 35 divh reg1, reg2 2 35 35 35 divh reg1, reg2, reg3 4 35 35 35 arithmetic operation instructions divhu reg1, reg2, reg3 4 34 34 34
chapter 5 instruction 131 user?s manual u15943ej3v0um table 5-6. list of number of in struction execution clock cycles (2/3) number of execution clocks type of instruction mnemonic operand byte i r l divu reg1, reg2, reg3 4 34 34 34 mov reg1, reg2 2 1 1 1 mov imm5, reg2 2 1 1 1 mov imm32, reg1 6 2 2 2 movea imm16, reg1, reg2 4 1 1 1 movhi imm16, reg1, reg2 4 1 1 1 sasf cccc, reg2 4 1 1 1 setf cccc, reg2 4 1 1 1 sub reg1, reg2 2 1 1 1 arithmetic operation instructions subr reg1, reg2 2 1 1 1 satadd reg1, reg2 2 1 1 1 satadd imm5, reg2 2 1 1 1 satsub reg1, reg2 2 1 1 1 satsubi imm16, reg1, reg2 4 1 1 1 saturated operation instructions satsubr reg1, reg2 2 1 1 1 and reg1, reg2 2 1 1 1 andi imm16, reg1, reg2 4 1 1 1 bsh reg2, reg3 4 1 1 1 bsw reg2, reg3 4 1 1 1 hsw reg2, reg3 4 1 1 1 not reg1, reg2 2 1 1 1 or reg1, reg2 2 1 1 1 ori imm16, reg1, reg2 4 1 1 1 sar reg1, reg2 4 1 1 1 sar imm5, reg2 2 1 1 1 shl reg1, reg2 4 1 1 1 shl imm5, reg2 2 1 1 1 shr reg1, reg2 4 1 1 1 shr imm5, reg2 2 1 1 1 sxb reg1 2 1 1 1 sxh reg1 2 1 1 1 tst reg1, reg2 2 1 1 1 xor reg1, reg2 2 1 1 1 xori imm16, reg1, reg2 4 1 1 1 zxb reg1 2 1 1 1 logical operation instructions zxh reg1 2 1 1 1 disp9 (when condition is satisfied) 2 2 note 3 2 note 3 2 note 3 branch instructions bcond disp9 (when condition is not satisfied) 2 1 1 1
chapter 5 instruction 132 user?s manual u15943ej3v0um table 5-6. list of number of in struction execution clock cycles (3/3) number of execution clocks type of instruction mnemonic operand byte i r l jarl disp22, reg2 4 2 note 4 2 note 4 2 note 4 jmp [reg1] 2 3 note 4 3 note 4 3 note 4 branch instructions jr disp22 4 2 note 4 2 note 4 2 note 4 clr1 bit#3, disp16 [reg1] 4 3 note 5 3 note 5 3 note 5 clr1 reg2, [reg1] 4 3 note 5 3 note 5 3 note 5 not1 bit#3, disp16 [reg1] 4 3 note 5 3 note 5 3 note 5 not1 reg2, [reg1] 4 3 note 5 3 note 5 3 note 5 set1 bit#3, disp16 [reg1] 4 3 note 5 3 note 5 3 note 5 set1 reg2, [reg1] 4 3 note 5 3 note 5 3 note 5 tst1 bit#3, disp16 [reg1] 4 3 note 5 3 note 5 3 note 5 bit manipulation instructions tst1 reg2, [reg1] 4 3 note 5 3 note 5 3 note 5 callt imm6 2 4 note 4 4 note 4 4 note 4 ctret ? 4 3 note 4 3 note 4 3 note 4 di ? 4 1 1 1 dispose imm5, list12 4 n+1 note 6 n+1 note 6 n+1 note 6 dispose imm5, list12, [reg1] 4 n+3 note 6 n+3 note 6 n+3 note 6 ei ? 4 1 1 1 halt ? 4 1 1 1 ldsr reg2, regid 4 1 1 1 nop ? 2 1 1 1 prepare list12, imm5 4 n+1 note 6 n+1 note 6 n+1 note 6 prepare list12, imm5, sp 4 n+2 note 6 n+2 note 6 n+2 note 6 prepare list12, imm5, imm16 6 n+2 note 6 n+2 note 6 n+2 note 6 prepare list12, imm5, imm32 8 n+3 note 6 n+3 note 6 n+3 note 6 reti ? 4 3 note 4 3 note 4 3 note 4 stsr regid, reg2 4 1 1 1 switch reg1 2 5 5 5 special instructions trap vector 4 3 note 4 3 note 4 3 note 4 dbret ? 4 3 note 4 3 note 4 3 note 4 debug function instructions dbtrap ? 2 3 note 4 3 note 4 3 note 4 undefined instruction code 4 3 3 3 notes 1. depends on the number of wait st ates (2 if no wait states). 2. depends on the number of wait st ates (1 if no wait states). 3. 3 if there is an instruction rewriti ng the psw contents i mmediately before. 4. +1 clock for type b products. 5. in case of no wait states (3 + number of read access wait states). 6. n is the total number of cycles to load registers in list12 (depends on the number of wait states, n is the number of registers in list12 if no wait states . the operation when n = 0 is the same as when n = 1).
chapter 5 instruction 133 user?s manual u15943ej3v0um remarks 1. operand convention symbol meaning reg1 general-purpose register (u sed as source register) reg2 general-purpose register (m ainly used as destination regist er. some are also used as source registers.) reg3 general-purpose register (mai nly used as remainder of divi sion results or higher 32 bits of multiply results) bit#3 3-bit data for bit number specification imm -bit immediate data disp -bit displacement data regid system register number vector 5-bit data for trap vector (00h to 1fh) specification cccc 4-bit data condition code specification sp stack pointer (r3) ep element pointer (r30) list list of registers ( is a maximum number of registers) 2. execution clock convention symbol meaning i when other instruction is executed immediat ely after executing an instruction (issue) r when the same instruction is repeatedly exec uted immediately after the instruction has been executed (repeat) l when a subsequent instruction uses the result of execution of the preceding instruction immediately after its execution (latency)
134 user?s manual u15943ej3v0um chapter 6 interrupts and exceptions interrupts are events that occur i ndependently of the program ex ecution and are divided into two types: maskable interrupts and non-maskable interrupts (nmi). in contra st, exceptions are events whose occurrence is dependent on the program execution and are divided into three types: software except ion, exception trap, and debug trap. when an interrupt or exception occurs, control is tr ansferred to a handler whose address is determined by the source of the interrupt or e xception. the source of the interrupt/exception is specif ied by the except ion code that is stored in the exception cause regi ster (ecr). each handler analyzes the ecr register and performs appropriate interrupt servicing or exception processi ng. the restore pc and restore psw are written to the status saving registers (eipc, eipsw or fepc, fepsw). to restore execution from interrupt or software exception processing, use the reti instruction. to restore execution from exception trap or debug tr ap, use the dbret instruction. read the restore pc and restore psw from the status saving register, and trans fer control to the restore pc. table 6-1. interrupt/exception codes interrupt/exception source name trigger classification exception code handler address restore pc nmi0 input interrupt 0010h 00000010h next pc note 2 nmi1 input interrupt 0020h 00000020h next pc notes 2, 3 non-maskable interrupt (nmi) note 1 nmi2 input note 4 interrupt 0030h 00000030h next pc notes 2, 3 maskable interrupt note 5 interrupt note 5 note 6 next pc note 2 trap0n (n = 0 to fh) trap instruction exception 004nh 00000040h next pc software exception trap1n (n = 0 to fh) trap instruction exception 005nh 00000050h next pc exception trap (ilgop) illegal instruction code exception 0060h 00000060h next pc note 7 debug trap dbtrap instruction exception 0060h 00000060h next pc notes 1. the trigger of the non-maskable interrupt incorporated differs depending on the product. 2. except when an interrupt is ack nowledged during execution of the one of the instructions listed below (if an interrupt is acknowledged during instruction execution, execution is stopped, and then resumed after the completion of interrupt servicing. in th is case, the address of t he stopped instruction is the restored pc.). ? load instructions (sld.b, sld.bu, sld.h, sld. hu, sld.w), divide instructions (div, divh, divu, divhu) ? prepare, dispose instruction (only if an inte rrupt is generated before the stack pointer is updated) 3. the pc cannot be restored by the re ti instruction. perform a system reset after interrupt servicing. 4. acknowledged even if the np flag of psw is set to 1. 5. differs depending on the type of the interrupts. 6. higher 16 bits are 0000h and lower 16 bits ar e the same value as the exception code. 7. the execution address of t he illegal instruction is obtained by ?restore pc ? 4?. remark restore pc: pc value saved to the eipc or f epc when interrupt/exception processing is started next pc: pc value that starts proce ssing after interrupt/exception processing
chapter 6 interrupts and exceptions 135 user?s manual u15943ej3v0um 6.1 interrupt servicing 6.1.1 maskable interrupt the maskable interrupt can be masked by the interrupt control register of the interrupt controller (intc). the intc issues an interrupt request to the cpu, bas ed on the acknowledged interrupt with the highest priority. if a maskable interrupt occurs due to interrupt request i nput (int input), the cpu per forms the following steps, and transfers control to the handler routine. (1) saves restore pc to eipc. (2) saves current psw to eipsw. (3) writes exception code to lower halfword of ecr (eicc). (4) sets id flag of psw to 1 and clears ep flag to 0. (5) sets handler address for each interrupt to pc and transfers control. the eipc and eipsw are used as the status saving registers. int i nputs are held pending in the interrupt controller (intc) when one of the follo wing two conditions occur: when the in t input is masked by its interrupt controller, or when an interrupt service routine is currently being executed (when the np flag of the psw is 1 or when the id flag of the psw is 1). interrupts are enabled by clear ing the mask condition or by setting the np and id flags of the psw to 0 with the ldsr instruct ion, which will be enabling new maskable interrupt servicing by a pending int input. the eipc and eipsw registers must be saved by program to enable nesting of interrupts because there is only one set of eipc and eipsw is provided. maskable interrupt servicing format is shown below.
chapter 6 interrupts and exceptions 136 user?s manual u15943ej3v0um figure 6-1. maskable interrupt servicing format interrupt request input (int input) xxif = 1 no interrupt request? xxmk = 0 no is the interrupt mask released? yes yes no no no maskable interrupt request interrupt request pending psw.np = 0 psw.id = 0 no no interrupt servicing pending yes yes interrupt servicing cpu processing intc processing yes yes yes priority higher than that of interrupt currently serviced? priority higher than that of other interrupt request? highest default priority of interrupt requests with the same priority? eipc eipsw ecr.eicc psw.ep psw.id pc restore pc psw exception code 0 1 handler address
chapter 6 interrupts and exceptions 137 user?s manual u15943ej3v0um 6.1.2 non-maskable interrupt the non-maskable interrupt cannot be di sabled by an instructi on and therefore can alwa ys be acknowledged. the non-maskable interrupt is generated by the nmi input. when the non-maskable interrupt is gener ated, the cpu performs the following steps, and transfers control to the handler routine. (1) saves restore pc to fepc. (2) saves current psw to fepsw. (3) writes exception code (0010h) to higher halfword of ecr (fecc). (4) sets np and id flags of psw to 1 and clears ep flag to 0. (5) sets handler address for the non-maskable interrupt to pc and transfers control. the fepc and fepsw are used as t he status saving registers. non-maskable interrupts are held pending in the interr upt controller when another non-maskable interrupt is currently being executed (when the np fl ag of the psw is 1). non-maskable interrupts are enabled by setting the np flag of the psw to 0 with the reti and ldsr instructions, which will be enabling new non-maskable interrupt servicing by a pending non-maskable interrupt request. in the case of products that inco rporate an interrupt trigger for nmi2 , only when nmi2 is generated during the interrupt servicing of nmi0 and nmi1, nmi2 servici ng is executed regardless of the value of np flag. non-maskable interrupt servicing format is shown below. figure 6-2. non-maskable interrupt servicing format psw.np = 0 fepc fepsw ecr.fecc psw.np psw.ep psw.id pc restore pc psw exception code 1 0 1 handler address no yes nmi input interrupt servicing interrupt request pending intc acknowledgement cpu processing non-maskable interrupt request
chapter 6 interrupts and exceptions 138 user?s manual u15943ej3v0um 6.2 exception processing 6.2.1 software exception a software exception is generated when the trap inst ruction is executed and is always acknowledged. if a software exception occurs, the cpu performs the follo wing steps, and transfers contro l to the handler routine. (1) saves restore pc to eipc. (2) saves current psw to eipsw. (3) writes exception code to lower 16 bi ts (eicc) of ecr (interrupt source). (4) sets ep and id flags of psw to 1. (5) sets handler address (00000040h or 00000050h) for softw are exception to pc and transfers control. software exception processing format is shown below. figure 6-3. software exception processing format eipc eipsw ecr.eicc psw.ep psw.id pc restore pc psw exception code 1 1 handler address trap instruction cpu processing exception processing
chapter 6 interrupts and exceptions 139 user?s manual u15943ej3v0um 6.2.2 exception trap an exception trap is an exception requested when an instruction is illega lly executed. the illegal opcode trap (ilgop) is the exception trap. an illegal opcode instruction has an instruction c ode with an opcode (bits 10 thr ough 5) of 111111b and a sub- opcode (bits 26 through 23) of 0111b thr ough 1111b and a sub-opcode (bit 16) of 0b. when this kind of an illegal opcode instruction is executed, an exception trap occurs. figure 6-4. illegal instruction code 011 1 111 1 0 15 13 12 11 10 5 4 0 31 27 26 23 22 21 20 17 16 111111 to remark : don?t care, : opcode/sub-opcode if an exception trap occurs, the cpu performs the followi ng steps, and transfers contro l to the handler routine. (1) saves restore pc to dbpc. (2) saves current psw to dbpsw. (3) sets np, ep, and id flags of psw to 1. (4) sets handler address (00000060h) for except ion trap to pc and transfers control. exception trap processing format is shown below. figure 6-5. exception trap processing format dbpc dbpsw psw.np psw.ep psw.id pc restore pc psw 1 1 1 00000060h exception trap (ilgop) occurs cpu processing exception processing caution the operation when executing the instruction not defined as an instruction or illegal instruction is not guaranteed. remark the execution address of t he illegal instruction is obtained by ?restore pc ? 4?.
chapter 6 interrupts and exceptions 140 user?s manual u15943ej3v0um 6.2.3 debug trap a debug trap is an exception generated when the dbtrap in struction is executed or when a debug function trap occurs, and is always acknowledged. if a debug trap occurs, the cpu performs the following steps. (1) saves restore pc to dbpc. (2) saves current psw to dbpsw. (3) sets np, ep, and id flags of psw to 1. (4) sets dm flag of dir to 1. (5) sets handler address (00000060h) for debug trap to pc and transfers control. debug trap processing format is shown below. figure 6-6. debug trap processing format dbpc dbpsw psw.np psw.ep psw.id dir.dm pc restore pc psw 1 1 1 1 00000060h dbtrap instruction cpu processing debug monitor routine processing
chapter 6 interrupts and exceptions 141 user?s manual u15943ej3v0um 6.3 restoring from interrupt/exception processing 6.3.1 restoring from interrupt and software exception all restoration from interrupt servicing and software exception is executed by the reti instruction. with the reti instruction, the cpu performs the following steps, and transfers control to the addre ss of the restore pc. (1) if the ep flag of the psw is 0 and the np flag of t he psw is 1, the restore pc and psw are read from the fepc and fepsw. otherwise, the restore pc and psw are read from the eipc and eipsw. (2) control is transferred to t he address of the restored pc and psw. when execution has returned from each interrupt servicing, the np and ep fl ags of the psw must be set to the following values by using the ldsr instru ction immediately before the reti instruction, in or der to restore the pc and psw normally: ? to restore from non-maskable interrupt se rvicing: np flag of psw = 1, ep flag = 0 ? to restore from maskable interrupt serv icing: np flag of psw = 0, ep flag = 0 ? to restore from exception processing: ep flag of psw = 1 restoration from interrupt/exception processing format is shown below. figure 6-7. restoration from inte rrupt/software exception processing format psw.ep = 0 psw.np = 0 pc psw eipc eipsw no pc psw fepc fepsw no yes yes reti instruction jump to address of restore pc
chapter 6 interrupts and exceptions 142 user?s manual u15943ej3v0um 6.3.2 restoring from excepti on trap and debug trap restoration from exception trap and debug trap is executed by the dbret instruction. with the dbret instruction, the cp u performs the following steps, and transfe rs control to the address of the restore pc. (1) the restore pc and psw are read from the dbpc and dbpsw. (2) control is transferred to the address of the restored pc and psw. (3) if restoring from exception trap or debug tr ap, the dm flag of dir is cleared to 0. restoration from exception trap/debug tr ap processing format is shown below. figure 6-8. restoration from excep tion trap/debug trap processing format pc psw dir.dm dbpc dbpsw 0 dbret instruction jump to address of restore pc
143 user?s manual u15943ej3v0um chapter 7 reset 7.1 register status after reset when a low-level signal is input to t he reset pin, the system is reset, and program registers and system registers are set in the status shown in table 7-1. when the reset signal goes high, t he reset status is cleared, and program execution begins. if necessary, initialize the c ontents of each register by program control. table 7-1. register status after reset register status after reset (initial value) general-purpose regist er (r0) 00000000h (fixed) general-purpose register (r1 to r31) undefined program registers program counter (pc) 00000000h interrupt status saving register (eipc) 0xxxxxxxh interrupt status saving register (eipsw) 00000xxxh nmi status saving register (fepc) 0xxxxxxxh nmi status saving register (fepsw) 00000xxxh exception cause register (ecr) 00000000h program status word (psw) 00000020h callt caller status saving register (ctpc) 0xxxxxxxh callt caller status saving register (ctpsw) 00000xxxh exception/debug trap status sa ving register (dbpc) 0xxxxxxxh exception/debug trap status sa ving register (dbpsw) 00000xxxh callt base pointer (ctbp) 0xxxxxxxh system registers debug interface register (dir) 00000000h remark x: undefined 7.2 starting up the cpu begins program execution from address 00000000h after it has been reset. after reset, no immediate interrupt requests are acknowl edged. to enable interrupts by program, clear the id flag of the psw to 0.
144 user?s manual u15943ej3v0um chapter 8 pipeline the v850es cpu is based on the risc ar chitecture and executes almost all the instructions in one clock cycle under control of a 5-stage pipeli ne. the instruction executi on sequence usually consists of five stages including fetch (if) to write back (wb) stages. the execution time of each stage differs depending on the type of the instruction and the type of the memory to be accessed. as an example of pipeline operation, figure 8-1 shows the processing of the cpu when 9 standard instructions are executed in succession. figure 8-1. example of executi ng nine standard instructions if id ex mem wb <1> <2> <3> <4> <5> if id ex mem wb if id ex mem wb if id ex mem wb if id ex mem wb if id ex mem wb <6> <7> <8> <9> <10> if id ex mem wb if id ex mem wb if id ex mem wb <11> <12> <13> instruction 1 ...................................... ............................ ...... ................. ................................................. ............................................................ ...................................................................... ................................................................................. ........................................................................................... processing cpu performs simultaneously internal system clock time flow (state) executes instruction every 1 clock cycle instruction 2 instruction 3 instruction 4 instruction 5 instruction 6 instruction 7 instruction 8 instruction 9 end of instruc- tion 1 end of instruc- tion 9 end of instruc- tion 8 end of instruc- tion 7 end of instruc- tion 6 end of instruc- tion 5 end of instruc- tion 4 end of instruc- tion 3 end of instruc- tion 2 if (instruction fetch): instruction is fetched and fetch pointer is incremented. id (instruction decode): instruction is decoded, i mmediate data is generated, and register is read. ex (execution of alu, multiplier, and barrel sh ifter): the decoded instru ction is executed. mem (memory access): the memory at specified address is accessed. wb (write back): the result of ex ecution is written to register. <1> through <13> in the figure above indica te the states of the cpu. in each state, write back (wb) of instruction n, memory access (mem) of instruction n+ 1, execution (ex) of in struction n+2, decoding (id) of instruction n+3, and fetching (if) of instruction n+4 ar e simultaneously performed. it takes five clock cycles to process a standard instruction, including if stage to wb st age. because five instructions can be processed at the same time, however, a standard instruction can be execut ed in 1 clock on the average.
chapter 8 pipeline 145 user?s manual u15943ej3v0um 8.1 features the v850es cpu, by optimizing the pipeline, improves the cpi (cycle per in struction) rate over the previous v850 cpu. the pipeline configurati on of the v850es cpu is shown in figure 8-2. figure 8-2. pipeline configuration id ex df wb wb mem bcond / sld pipeline id if address calculation stage asynchronous wb pipeline master pipeline (v850 cpu compatible) load, store buffer (1 stage each) remark df (data fetch): execution dat a is transferred to the wb stage.
chapter 8 pipeline 146 user?s manual u15943ej3v0um 8.1.1 non-blocking load/store as the pipeline does not stop during external memory access, efficient processing is possible. for example, figure 8-3 shows a comparison of pipe line operations between the v850 cpu and the v850es cpu when an add instruction is executed after the execution of a load in struction for external memory. figure 8-3. non-blocking load/store (a) previous version (v850 cpu): pipeline is stopped until mem stage is complete if id ex t1 mem (external memory) note t2 t3 wb if id ex (mem) wb if id mem wb ex load instruction add instruction next instruction note the basic bus cycle for the external memory is 3 clocks. (b) v850es cpu: efficient pipeline pro cessing through use of asynchronous wb pipeline if id ex t1 mem (external memory) n o te t2 wb if id ex wb df if id ex wb mem load instruction add instruction next instruction note the basic bus cycle for the external memory of memc is 2 clocks. (1) v850 cpu the ex stage of the add instru ction is usually executed in 1 clock. however, a wait time is generated in the ex stage of the add instruction during ex ecution of the mem stage of the previous load in struction. this is because the same stage of the 5 instru ctions on the pipeline cannot be exec uted in the same internal clock interval. this also causes a wait time to be generat ed in the id stage of the nex t instruction after the add instruction. (2) v850es cpu an asynchronous wb pipeline for the instructions t hat are necessary for the mem stage is provided in addition to the master pipeline. the mem stage of the load instructi on is therefore processed on this asynchronous wb pipeline. because t he add instruction is processed on the master pipeline, a wait time is not generated, making it possible to execute instructions efficient ly as shown in figure 8-3.
chapter 8 pipeline 147 user?s manual u15943ej3v0um 8.1.2 2-clock branch when executing a branch instruct ion, the branch destination is decided in the id stage. in the case of the conventional v850 cpu, the branch destination of when t he branch instruction is executed was decided after execution of the ex stage, but in the case of the v850es cpu, due to the addition of a address calculation stage for branch/sld instruct ion, the branch destination is decided in the id stage. t herefore, it is possible to fetch the branch destination instruction 1 clock faster than in t he conventional v850 cpu. figure 8-4 shows a comparison betw een the v850 cpu and the v850es cpu of pipeline operations with branch instructions. figure 8-4. pipeline operati ons with branch instructions (a) previous version (v850 cpu) if id ex wb branch instruction branch destination instruction if id ex wb mem mem branch destination decided in ex stage 3 clocks (b) v850es cpu if id wb if id ex wb mem mem branch destination decided in id stage ex branch instruction branch destination instruction 2 clocks remark type b product executes interleave access to the internal flash memory or internal mask rom. therefore, it takes two clocks to fetch an instruction immediately afte r an interrupt has occurred or after a branch destination instruction has been executed. consequently, it ta kes three clocks to execute the id stage of the branch des tination instruction. example if if id ex mem wb if if id ex mem wb if if id if if id ex mem wb if if id ex mem wb instruction 1 instruction 2 instruction 3 branch instruction branch destination instruction interleave access 3 clocks
chapter 8 pipeline 148 user?s manual u15943ej3v0um 8.1.3 efficient pipeline processing because the v850es cpu has an id stage for branch/sld in structions in addition to the id stage on the master pipeline, it is possible to perform efficient pipeline processing. figure 8-5 shows an example of a pipe line operation where the next branch inst ruction was fetched in the if stage of the add instruction (instruction fetc h from the rom directly connected to the dedicated bus is performed in 32-bit units. both add instructions and branch instructi ons in figure 8-5 use a 16-bit format instruction). figure 8-5. parallel execution of branch instructions (a) previous version (v850 cpu) if id id ex if ex (mem) wb mem wb if id ex mem add instruction branch instruction branch destination instruction 5 clocks (b) v850es cpu if id ex df wb mem wb if id ex mem id wb ex add instruction branch instruction branch destination instruction 3 clocks if (1) v850 cpu although the instruction codes up to the next branch instruction are fe tched in the if stage of the add instruction, the id stage of the add instruction and the id stage of the branch instruction cannot execute together within the same clo ck. therefore, it takes 5 clocks from the branch instruction fetch to the branch destination instruction fetch. (2) v850es cpu because v850es cpu has an id stage for branch/sld inst ructions in addition to t he id stage on the master pipeline, the parallel execution of the id stage of the add instruct ion and the id stage of the branch instruction within the same clock is possible. therefore, it takes only 3 clocks from the branch instruction fetch start to the branch desti nation instruction completion. caution be aware that the sld and bcond instruct ions are sometimes execute d at the same time as other 16-bit format instructions. for example, if the sld and nop instructions are executed simultaneously, the nop inst ruction may keep the delay ti me from bei ng generated.
chapter 8 pipeline 149 user?s manual u15943ej3v0um 8.2 pipeline flow during execution of instructions this section explains the pipeline flow during the execution of instructions. in pipeline processing, the cpu is already processing t he next instruction when the memory or i/o write cycle is generated. as a result, i/o manipulations and interrupt r equest masking will be reflected later than next instructions are issued (id stage). when an interrupt mask manipulation is performed, mask able interrupt acknowledgement is disabled from the instruction immediately after an inst ruction because the cpu detects access to the internal intc (id stage) and performs interrupt request mask processing. 8.2.1 load instructions caution due to non-blocking control, there is no guara ntee that the bus cycle is complete between the mem stages. however, when accessing the peripheral i/o area, bl ocking control is effected, making it possible to wait for the e nd of the bus cycle at the mem stage. (1) ld instructions [instructions] ld.b, ld.bu, ld.h, ld.hu, ld.w [pipeline] <1> <2> <3> <4> <5> <6> ld instruction if id ex mem wb next instruction if id ex mem wb [description] the pipeline consists of 5 stages, if , id, ex, mem, and wb. if an instruction using the execution result is placed immediately after the ld instruction, data wait time occurs. (2) sld instructions [instructions] sld.b, sld. bu, sld.h, sld.hu, sld.w [pipeline] <1> <2> <3> <4> <5> <6> sld instruction if id mem wb next instruction if id ex mem wb [description] the pipeline consists of 4 stages, if, id , mem, and wb. if an instruction using the execution result is placed immediately after the sl d instruction, data wait time occurs.
chapter 8 pipeline 150 user?s manual u15943ej3v0um 8.2.2 store instructions caution due to non-blocking control, there is no guara ntee that the bus cycle is complete between the mem stages. however, when accessing the peripheral i/o area, bl ocking control is effected, making it possible to wait for the e nd of the bus cycle at the mem stage. [instructions] st.b, st.h, st.w, sst.b, sst.h, sst.w <1> <2> <3> <4> <5> <6> [pipeline] store instruction if id ex mem wb next instruction if id ex mem wb [description] the pipeline consists of 5 stages, if , id, ex, mem, and wb. however, no operation is performed in the wb stage, because no data is written to registers. 8.2.3 multiply instructions (1) halfword data multiply instruction [instructions] mulh, mulhi [pipeline] (a) when next instructi on is not multiply instruction <1> <2> <3> <4> <5> <6> multiply instruction if id ex1 ex2 wb next instruction if id ex mem wb (b) when next instruction is multiply instruction <1> <2> <3> <4> <5> <6> multiply instruction 1 if id ex1 ex2 wb multiply instruction 2 if id ex1 ex2 wb [description] the pipeline consists of 5 stages, if, id, ex1, ex2, and wb. the ex stage takes 2 clocks because it is executed by a mu ltiplier. ex1 and ex2 stages (d ifferent from the normal ex stage) can operate independently . therefore, the number of clo cks for instruction execution is always 1 clock, even if several multiply instruct ions are executed in a row. however, if an instruction using the execution resu lt is placed immediately after a multiply instruction, data wait time occurs.
chapter 8 pipeline 151 user?s manual u15943ej3v0um (2) word data multiply instructions [instructions] mul, mulu [pipeline] (a) when the next three instru ctions are not multiply instructions <1> <2> <3> <4> <5> <6> <7> <8> multiply instruction if id ex1 ex1 ex1 ex1 ex2 wb instruction 1 if id ex mem wb instruction 2 if id ex mem wb instruction 3 if id ex mem wb (b) when the next instruction is a multiply instruction <1> <2> <3> <4> <5> <6> <7> <8> <9> multiply instruction 1 if id ex1 ex1 ex1 ex1 ex2 wb multiply instruction 2 if ? ? ? id ex1 ex2 wb (halfword) ?: idle inserted for wait (c) when the instruction following the next tw o instructions is a multiply instruction <1> <2> <3> <4> <5> <6> <7> <8> <9> multiply instruction 1 if id ex1 ex1 ex1 ex1 ex2 wb instruction 1 if id ex mem wb instruction 2 if id ex mem wb multiply instruction 2 if ? id ex1 ex2 wb (halfword) ?: idle inserted for wait [description] the pipeline consists of 8 stages, if, id, ex1 (4 stages), ex2, and wb. the ex stage takes 5 clocks because it is executed by a multiplier. ex1 and ex2 stages (different from the normal ex stage) can operate independently. t herefore, the number of clo cks for instruction execution is always 4 clocks, even if several multiply instru ctions are executed in a row. however, if an instruction using the execution resu lt is placed immediately after a multiply instruction, data wait time occurs.
chapter 8 pipeline 152 user?s manual u15943ej3v0um 8.2.4 arithmetic operation instructions (1) instructions other than di vide/move word instructions [instructions] add, addi, cmov, cmp, mo v, movea, movhi, sasf, setf, sub, subr <1> <2> <3> <4> <5> <6> [pipeline] arithmetic operation instruction if id ex df wb next instruction if id ex mem wb [description] the pipeline consists of 5 stages, if, id, ex, df, and wb. (2) move word instruction [instructions] mov imm32 <1> <2> <3> <4> <5> <6> <7> [pipeline] arithmetic operation instruction if id ex1 ex2 df wb next instruction if ? id ex mem wb ?: idle inserted for wait [description] the pipeline consists of 6 st ages, if, id, ex1, ex2 (normal ex stage), df, and wb. (3) divide instructions [instructions] div, divh, divhu, divu [pipeline] (a) div, divh instructions <1> <2> <3> <4> <35> <36> <37> <38> <39> <40> <41> divide instruction if id ex1 ex2 ex33 ex34 ex35 df wb next instruction if ? ? ? ? id ex mem wb next to next instruction if id ex mem wb ?: idle inserted for wait (b) divhu, divu instructions <1> <2> <3> <4> <35> <36> <37> <38> <39> <40> divide instruction if id ex1 ex2 ex33 ex34 df wb next instruction if ? ? ? id ex mem wb next to next instruction if id ex mem wb ?: idle inserted for wait [description] the pipeline consists of 39 stages, if, id, ex1 to ex35 (normal ex stage), df, and wb for div and divh instructions. the pipeline consists of 38 stages, if, id, ex1 to ex34 (normal ex stage), df, and wb for divhu and divu instructions. [remark] if an interrupt occurs while a division instru ction is executed, executi on of the instruction is stopped, and the interrupt is proce ssed, assuming that the return address is the first address of that instruction. after interrupt servicing has been completed, the di vision instruction is executed again. in this case, general-purpos e registers reg1 and reg2 hold the value before the instruction is executed.
chapter 8 pipeline 153 user?s manual u15943ej3v0um 8.2.5 saturated operation instructions [instructions] satadd, satsub, satsubi, satsubr <1> <2> <3> <4> <5> <6> [pipeline] saturated operation instruction if id ex df wb next instruction if id ex mem wb [description] the pipeline consists of 5 stages, if, id, ex, df, and wb. 8.2.6 logical operation instructions [instructions] and, andi, bsh, bsw, hsw, not, or , ori, sar, shl, shr, sxb, sxh, tst, xor, xori, zxb, zxh <1> <2> <3> <4> <5> <6> [pipeline] logical operation instruction if id ex df wb next instruction if id ex mem wb [description] the pipeline consists of 5 stages, if, id, ex, df, and wb. 8.2.7 branch instructions (1) conditional branch instruct ions (except br instruction) [instructions] bcond instructions (bc, be, bge, bgt, bh, bl, ble, blt, bn, bnc, bne, bnh, bnl, bnv, bnz, bp, bsa, bv, bz) [pipeline] (a) when the condition is not satisfied <1> <2> <3> <4> <5> <6> conditional branch instruction if id ex mem wb next instruction if id ex mem wb (b) when the condition is satisfied <1> <2> <3> <4> <5> <6> <7> conditional branch instruction if id ex mem wb next instruction (if) branch destination instruction if id ex mem wb (if): instruction fetch that is not executed
chapter 8 pipeline 154 user?s manual u15943ej3v0um [description] the pipeline consists of 5 stages, if , id, ex, mem, and wb. however, no operation is performed in the ex, mem, and wb stages, becaus e the branch destinati on is decided in the id stage. (a) when the condition is not satisfied the number of execution clocks fo r the branch instruction is 1. (b) when the condition is satisfied the number of execution cl ocks for the branch instruction is 2. if stage of the next instruction of the branch in struction is not executed. if an instruction overwriting the contents of psw occurs imm ediately before, the number of execution clocks is 3 because of flag hazard occurrence. (2) br instruction, unconditional branch instructions (except jmp instruction) [instructions] br, jarl, jr [pipeline] <1> <2> <3> <4> <5> <6> <7> br instruction, unconditional branch instruction if id ex mem wb* next instruction (if) branch destination instruction if id ex mem wb (if): instruction fetch that is not executed wb*: no operation is performed in the case of the jr and br instructions but in the case of the jarl instruct ion, data is writt en to the restore pc. [description] the pipeline consists of 5 stages, if , id, ex, mem, and wb. however, no operation is performed in the ex, mem, and wb stages, becaus e the branch destinati on is decided in the id stage. however, in the case of the jarl instructi on, data is written to the restore pc in the wb stage. also, the if stage of the next instruct ion of the branch instruct ion is not executed. (3) jmp instruction [pipeline] <1> <2> <3> <4> <5> <6> <7> jmp instruction if id ex mem wb next instruction (if) branch destination instruction if id ex mem wb (if): instruction fetch that is not executed [description] the pipeline consists of 5 stages, if , id, ex, mem, and wb. however, no operation is performed in the ex, mem, and wb stages, becaus e the branch destinati on is decided in the id stage.
chapter 8 pipeline 155 user?s manual u15943ej3v0um 8.2.8 bit manipulation instructions (1) clr1, not1, set1 instructions [pipeline] <1> <2> <3> <4> <5> <6> <7> <8> <9> bit manipulation instruction if id ex1 mem ex2 mem wb next instruction if ? ? id ex mem wb next to next instruction if id ex mem wb ?: idle inserted for wait [description] the pipeline consists of 7 stages, if , id, ex1, mem, ex2 (normal stage), mem, and wb. however, no operation is performed in the wb st age, because no data is wri tten to registers. in the case of these instructions, the me mory access is read modify write, the ex stage requires a total of 2 clocks, and the mem stage requires a total of 2 cycles. (2) tst1 instruction [pipeline] <1> <2> <3> <4> <5> <6> <7> <8> <9> bit manipulation instruction if id ex1 mem ex2 mem wb next instruction if ? ? id ex mem wb next to next instruction if id ex mem wb ?: idle inserted for wait [description] the pipeline consists of 7 stages, if , id, ex1, mem, ex2 (normal stage), mem, and wb. however, no operation is performed in the second mem and wb stages, because there is no second memory access nor data write to registers. in all, this instruction requires 2 clocks. 8.2.9 special instructions (1) callt instruction [pipeline] <1> <2> <3> <4> <5> <6> <7> <8> <9> callt instruction if id mem ex mem wb next instruction (if) branch destination instruction if id ex mem wb (if): instruction fetch that is not executed [description] the pipeline consists of 6 stages, if, id, mem, ex, mem, and wb. however, no operation is performed in the second mem and wb stages, because there is no memory access and no data is written to registers.
chapter 8 pipeline 156 user?s manual u15943ej3v0um (2) ctret instruction [pipeline] <1> <2> <3> <4> <5> <6> <7> ctret instruction if id ex mem wb next instruction (if) branch destination instruction if id ex mem wb (if): instruction fetch that is not executed [description] the pipeline consists of 5 stages, if , id, ex, mem, and wb. however, no operation is performed in the ex, mem, and wb stages, becaus e the branch destinati on is decided in the id stage. (3) di, ei instructions <1> <2> <3> <4> <5> <6> [pipeline] di, ei instruction if id ex mem wb next instruction if id ex mem wb [description] the pipeline consists of 5 stages, if , id, ex, mem, and wb. however, no operation is performed in the mem and wb stages, because memory is not accessed and data is not written to registers. [remark] both the di and ei instru ctions do not sample an interrupt r equest. an interrupt is sampled as follows while these inst ructions are executed. instruction imm ediately before if id ex mem wb di, ei instruction if id ex mem wb instruction immediately after if id ex mem wb last sampling of interrupt before execution of ei or di instruction first sampling of interrupt after execution of ei or di instruction
chapter 8 pipeline 157 user?s manual u15943ej3v0um (4) dispose instruction [pipeline] (a) when branch is not executed <1> <2> <3> <4> dispose instruction if id ex mem mem mem mem wb next instruction if ? ? ? id ex mem wb next to next instruction if id ex mem wb ?: idle inserted for wait n: number of registers specifi ed in the register list (list12) (b) when branch is executed <1> <2> <3> <4> dispose instruction if id ex mem mem mem mem wb next instruction (if) branch destination instruction if id ex (if): instruction fetch that is not executed ?: idle inserted for wait n: number of registers specifi ed in the register list (list12) [description] the pipeline consists of n + 5 stages (n: register list numbe r), if, id, ex, n + 1 times mem, and wb. the mem stage requires n + 1 cycles. (5) halt instruction [pipeline] <1> <2> <3> <4> <5> <6> halt mode release halt instruction if id ex mem wb next instruction if ? ? ? ? ? id ex mem wb next to next instruction if id ex mem wb [description] the pipeline consists of 5 stages, if, id, ex, mem and wb. no operation is performed in the mem and wb stages, because memory is not acce ssed and no data is written to registers. also, for the next instruction, the id stage is delayed until the halt mode is released. (6) ldsr, stsr instructions <1> <2> <3> <4> <5> <6> [pipeline] ldsr, stsr instruction if id ex df wb next instruction if id ex mem wb [description] the pipeline consists of 5 stages, if, id , ex, df, and wb. if the stsr instruction using the eipc and fepc system registers is placed imm ediately after the ldsr instruction setting these registers, data wait time occurs.
chapter 8 pipeline 158 user?s manual u15943ej3v0um (7) nop instruction <1> <2> <3> <4> <5> <6> [pipeline] nop instruction if id ex mem wb next instruction if id ex mem wb [description] the pipeline consists of 5 stages, if , id, ex, mem, and wb. however, no operation is performed in the ex, mem, and wb stages, because no operation and no memory access is executed, and no data is wr itten to registers. caution be aware that the sld and bcond instruct ions are sometimes execute d at the same time as other 16-bit format instructions. for example, if the sld and nop instructions are executed simultaneously, the nop inst ruction may keep the delay ti me from bei ng generated. (8) prepare instruction [pipeline] <1> <2> <3> <4> prepare instruction if id ex mem mem mem mem wb next instruction if ? ? ? id ex mem wb next to next instruction if id ex mem wb ?: idle inserted for wait n: number of registers specifi ed in the register list (list12) [description] the pipeline consists of n + 5 stages (n: register list numbe r), if, id, ex, n + 1 times mem, and wb. the mem stage requires n + 1 cycles. (9) reti instruction <1> <2> <3> <4> <5> <6> <7> <8> [pipeline] reti instruction if id1 id2 ex mem wb next instruction (if) next to next instruction (if) jump destination instruction if id ex mem wb (if): instruction fetch that is not executed id1: register selection id2: read eipc/fepc [description] the pipeline consists of 6 stages, if, id 1, id2, ex, mem, and wb. however, no operation is performed in the mem and wb stages, because memo ry is not accessed and no data is written to registers. the id stage requires 2 clocks. also, the if stages of the next instruction and next to next instruction are not executed.
chapter 8 pipeline 159 user?s manual u15943ej3v0um (10) switch instruction [pipeline] <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> switch instruction if id ex1 mem ex2 mem wb next instruction (if) branch destination instruction if id ex mem wb (if): instruction fetch that is not executed [description] the pipeline consists of 7 stages, if , id, ex1 (normal ex stage), mem, ex2, mem, and wb. however, no operation is performed in the second mem and wb stages, because there is no memory access and no data is written to registers. (11) trap instruction <1> <2> <3> <4> <5> <6> <7> <8> [pipeline] trap instruction if id1 id2 ex df wb next instruction (if) next to next instruction (if) jump destination instruction if id ex mem wb (if): instruction fetch that is not executed id1: exception code (004nh, 005nh) detection (n = 0 to fh) id2: address generation [description] the pipeline consists of 6 stages, if, id1, id2, ex, df, and wb. the id stage requires 2 clocks. also, the if stages of the next instruct ion and next to next instruct ion are not executed.
chapter 8 pipeline 160 user?s manual u15943ej3v0um 8.2.10 debug function instructions (1) dbret instruction <1> <2> <3> <4> <5> <6> <7> <8> [pipeline] dbret instruction if id1 id2 ex mem wb next instruction (if) next to next instruction (if) jump destination instruction if id ex mem wb (if): instruction fetch that is not executed id1: register selection id2: read dbpc [description] the pipeline consists of 6 stages, if, id 1, id2, ex, mem, and wb. however, no operation is performed in the mem and wb stages, because t he memory is not accessed and no data is written to registers. the id stage requires 2 clocks. also, the if stages of the next instruction and next to next instruct ion are not executed. (2) dbtrap instruction <1> <2> <3> <4> <5> <6> <7> <8> [pipeline] dbtrap instruction if id1 id2 ex df wb next instruction (if) next to next instruction (if) jump destination instruction if id ex mem wb (if): instruction fetch that is not executed id1: exception code (0060h) detection id2: address generation [description] the pipeline consists of 6 stages, if, id1, id2, ex, me m, and wb. the id stage requires 2 clocks. also, the if stages of the next instruct ion and next to next instru ction are not executed.
chapter 8 pipeline 161 user?s manual u15943ej3v0um 8.3 pipeline disorder the pipeline consists of 5 stages from if (instruction fetch) to wb (write back). each stage basically requires 1 clock for processing, but the pipeline ma y become disordered, causi ng the number of execution clocks to increase. this section describes the main causes of pipeline disorder. 8.3.1 alignment hazard if the branch destination instruction addre ss is not word aligned (a1 = 1, a0 = 0) and is 4 bytes in length, it is necessary to repeat if twice in order to align instructi ons in word units. this is called an align hazard. for example, the instructions a to e are placed from address x0h, and that in struction b consists of 4 bytes, and the other instructions each cons ist of 2 bytes. in this case, instruction b is placed at x2h (a1 = a0 = 0), and is not word aligned (a1 = 0, a0 = 0). theref ore, when this instruction b becomes t he branch destination in struction, an align hazard occurs. when an align hazard occu rs, the number of execution clocks of the branch instruction becomes 4. figure 8-6. align hazard example (a) memory map (b) pipeline if id ex mem wb if branch instruction next instruction <1> <2> <3> <4> <5> <6> <7> <8> if1 if2 id ex mem wb if id ex mem wb <9> branch destination instruction (instruction b) branch destination's next instruction (instruction c) instruc- tion d instruc- tion e instruc- tion b instruc- tion c instruc- tion a instruc- tion b x8h x4h x0h 32 bits address of branch destination instruction (instruction b) if : instruction fetch that is not executed if1: first instruction fetch that occurs during align hazard. it is a 2-byte fetch that fetches the 2 bytes on the lower address of instruction b. if2: second instruction fetch that occurs during align hazard. it is normally a 4-byte fetch that fetc hes the 2 bytes on the higher address of instruction b in addition to instruction c (2-byte length). align hazards can be prevented through t he following handling in order to obtain faster instruction execution. ? use 2-byte branch desti nation instruction. ? use 4-byte instructions placed at word boundaries (a 1 = 0, a0 = 0) for branch destination instructions.
chapter 8 pipeline 162 user?s manual u15943ej3v0um 8.3.2 referencing execution r esult of load instruction for load instructions (ld, sld), data read in the mem stage is saved during the wb stage. t herefore, if the contents of the same register are used by the instruction immediately after t he load instruction, it is necessary to delay the use of the register by this later instruction until the load inst ruction has ended using that r egister. this is called a hazard. the v850es cpu has an interlock functi on to automatically handle this hazard by delaying the id stage of the next instruction. the v850es cpu also has a short path that allows the data r ead during the mem stage to be used in the id stage of the next instruction. this shor t path allows data to be read with the l oad instruction during the mem stage and the use of this data in the id stage of the next instruction with the same timing. as a result of the above, when using t he execution result in the instruction following immediately after, the number of execution clocks of the load instruction is 2. figure 8-7. example of execution result of load instruction if id ex mem wb if il id ex mem load instruction 1 (ld [r4], r6) instruction 2 (add 2, r6) wb if - id ex mem if id ex mem wb wb instruction 3 instruction 4 <1> <2> <3> <4> <5> <6> <7> <8> <9> il: idle inserted for data wait by interlock function -: idle inserted for wait : short path as shown in figure 8-7, when an instruct ion placed immediately after a load inst ruction uses its execution result, a data wait time occurs due to the interl ock function, and the execut ion speed is lowered. th is drop in execution speed can be avoided by placing instruct ions that use the execution re sult of a load instruction at least 2 instructions after the load instruction.
chapter 8 pipeline 163 user?s manual u15943ej3v0um 8.3.3 referencing execution result of multiply instruction for multiply instructions, the operation resu lt is saved to the register in the wb stage. therefore, if the contents of the same register are used by t he instruction immediately after the multiply in struction, it is nece ssary to delay the use of the register by this later instru ction until the multiply in struction has ended using that register (occurrence of hazard). the v850es cpu?s interlock function dela ys the id stage of the instruction fo llowing immediately after. a short path is also provided that allo ws the ex2 stage of the multiply instruction and the multiply instruction?s operation result to be used in the id stage of the instruction fo llowing immediately after with the same timing. figure 8-8. example of execution result of multiply instruction (a) in the case of halfword data multiply instruction if id ex1 ex2 wb if il id ex mem instruction 2 (add 2, r6) wb if - id ex mem if id ex mem wb wb instruction 3 instruction 4 <1> <2> <3> <4> <5> <6> multiply instruction 1 (mulh 3, r6) <7> <8> <9> il: idle inserted for data wait by interlock function -: idle inserted for wait : short path (b) in the case of word data multiply instruction if id ex1 ex1 ex1 ex1 ex2 wb if il il il il instruction 2 (add 2, r6) id if-- -- if id ex mem wb id ex mem wb instruction 3 instruction 4 <1> <2> <3> <4> <5> <6> multiply instruction 1 (mulh 3, r6) <7> <8> <9> ex mem wb <10> <11> <12> il: idle inserted for data wait by interlock function -: idle inserted for wait : short path as shown in figure 8-8, when an instru ction placed immediately after a multip ly instruction uses its execution result, a data wait time occurs due to the interlock func tion, and the execution speed is lowered. this drop in execution speed can be avoided by placing inst ructions that use the exec ution result of a multiply instruction at least 2 instructions after the multiply instruction. however, in the case of the word dat a multiply instructions (mul, mulu), if the instruction that uses the result of the multiply instru ction is not place at least five instructions after the multiply instruction, an il stage is inserted between 1 and 4.
chapter 8 pipeline 164 user?s manual u15943ej3v0um 8.3.4 referencing execution result of ldsr instruction for eipc and fepc when using the ldsr instruction to set the data of the eipc and fepc syst em registers, and immediately after referencing the same system registers with the stsr instruction, the use of the system registers for the stsr instruction is delayed until the setting of the system registers with the ldsr in struction is completed (occurrence of hazard). the v850es cpu?s interlock function delays the id st age of the stsr instructi on immediately after. as a result of the above, when using t he execution result of the ldsr inst ruction for eipc and fepc for an stsr instruction following immediately after, the number of execution clocks of the ldsr instruction becomes 3. figure 8-9. example of referencing execution r esult of ldsr instruction for eipc and fepc if id ex mem if il il ex ldsr instruction (ldsr r6, 0) note stsr instruction (stsr 0, r7) note mem if - id ex mem if id ex mem wb wb next instruction next to next instruction wb wb id - <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> il: idle inserted for data wait by interlock function -: idle inserted for wait note system register 0 used for the ldsr and stsr instructions designates eipc. as shown in figure 8-9, when an stsr instruction is placed immediately afte r an ldsr instruction that uses the operand eipc or fepc, and that stsr inst ruction uses the ldsr instruction ex ecution result, the interlock function causes a data wait time to occur, and the execution speed is lowered. th is drop in execution speed can be avoided by placing stsr instructions that re ference the execution resu lt of the preceding ldsr instruction at least 3 instructions after the ldsr instruction. 8.3.5 cautions when creating programs when creating programs, pipeline di sorder can be avoided and instructi on execution speed can be raised by observing the following cautions. ? place instructions that use the execution result of load in structions (ld, sld) at l east 2 instructions after the load instruction. ? place instructions that use the execution result of mult iply instructions (mulh, mulhi) at least 2 instructions after the multiply instruction. ? if using the stsr instruction to r ead the setting results written to the ei pc or fepc registers with the ldsr instruction, place the stsr inst ruction at least 3 instructions after the ldsr instruction. ? for the first branch destination instruct ion, use a 2-byte instruction, or a 4-byte instruction placed at the word boundary.
chapter 8 pipeline 165 user?s manual u15943ej3v0um 8.4 additional items related to pipeline 8.4.1 harvard architecture the v850es cpu uses the harvard arch itecture to operate an instruction fetch path from internal rom and a memory access path to internal ram independently. this e liminates bus arbitration conflicts between the if and mem stages and allows orderly pipeline operation. (1) v850es cpu (harvard architecture) the mem stage of instruction 1 and the if stage of instruct ion 4, as well as the me m stage of instruction 2 and the if stage of instruction 5 can be executed simultaneously with orderly pipeline operation. if id ex mem if id ex wb instruction 1 instruction 2 if ex mem wb ex mem wb instruction 3 instruction 4 wb mem id instruction 5 id ex mem wb if if id <1> <2> <3> <4> <5> <6> <7> <8> <9> (2) not v850es cpu (other th an harvard architecture) the mem stage of instruction 1 and the if stage of instruct ion 4, in addition to the me m stage of instruction 2 and the if stage of instruction 5 are in contention, causi ng bus waiting to occur and slower execution time due to disorderly pipeline operation. if id ex mem if id - mem instruction 1 instruction 2 if id - ex - id ex instruction 3 instruction 4 wb ex - instruction 5 if if id ex <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> wb mem mem mem <11> wb wb wb -: idle inserted for wait
chapter 8 pipeline 166 user?s manual u15943ej3v0um 8.4.2 short path the v850es cpu provides on chip a s hort path that allows the use of t he execution result of the preceding instruction by the following instructi on before write back (wb) is complet ed for the previous instruction. example 1. execution result of arithmet ic operation instruction and logica l operation used by instruction following immediately after ? v850es cpu (on-chip short path) the execution result of the preceding instruction can be used for the id stage of the instruction following immediately after as soon as the result is out (ex stage), without having to wait for write back to be completed. if id ex mem wb if id ex mem wb add 2, r6 mov r6, r7 <1> <2> <3> <4> <5> <6> ? not v850es cpu (no short path) the id stage of the instructi on following immediately after is delayed until write back of the previous instruction is completed. if id ex wb if--idex add 2, r6 mov r6, r7 mem wb <1> <2> <3> <4> <5> <6> <7> <8> mem -: idle inserted for wait : short path
chapter 8 pipeline 167 user?s manual u15943ej3v0um example 2. data read from memory by the load instruction used by instruction following immediately after ? v850es cpu (on-chip short path) the execution result of the preceding instruction can be used for the id stage of the instruction following immediately after as soon as the result is out (mem stage), without having to wait for write back to be completed. if id ex mem wb if il id ex mem ld [r4], r6 add 2, r6 wb id ex mem id ex mem wb wb next instruction next to next instruction <1> <2> <3> <4> <5> <6> <7> <8> <9> if - if ? not v850es cpu (no short path) the id stage of the instructi on following immediately after is delayed until write back of the previous instruction is completed. if id ex mem wb if--idex ld [r4], r6 add 2, r6 mem if id ex if id ex mem mem next instruction next to next instruction wb wb wb <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> il: idle inserted for data wait by interlock function -: idle inserted for wait : short path
168 user?s manual u15943ej3v0um appendix a notes a.1 restriction on conflict between sl d instruction and interrupt request a.1.1 description if a conflict occurs between the decode oper ation of an instruction in <2> imm ediately before the sld instruction following an instruction in <1> and an interr upt request before the instru ction in <1> is complete, the execution result of the instruction in <1> ma y not be stored in a register. instruction <1> ? ld instruction: ld.b, ld.h, ld.w, ld.bu, ld.hu ? sld instruction: sld.b, sld.h, sld.w, sld.bu, sld.hu ? multiplication instruction: mul, mulh, mulhi, mulu instruction <2> mov reg1, reg2 satadd reg1, reg2 and reg1, reg2 add reg1, reg2 mulh reg1, reg2 not reg1, reg2 satadd imm5, reg2 tst reg1, reg2 add imm5, reg2 shr imm5, reg2 satsubr reg1, reg2 or reg1, reg2 subr reg1, reg2 cmp reg1, reg2 sar imm5, reg2 satsub reg1, reg2 xor reg1, reg2 sub reg1, reg2 cmp imm5, reg2 shl imm5, reg2 ld.w [r11], r10 if the decode operation of the mo v instruction immediately before the sld instruction and an interrupt request conflic t before execution of the ld instruction is complete, the execution result of in struction may not be stored in a register. mov r10, r28 sld.w 0x28, r10 a.1.2 countermeasure when executing the sld instruction imm ediately after instruction , avoid the above operation usi ng either of the following methods. ? insert a nop instruction immediat ely before the sld instruction. ? do not use the same register as t he sld instruction destination register in the above instruction executed immediately before t he sld instruction. ? ? ?
169 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
appendix b instruction list 170 user?s manual u15943ej3v0um table b-1. instruction function list (in alphabetical order) (2/11) flag mnemonic operand format cy ov s z sat instruction function clr1 reg2 [reg1] ix ? ? ? 0/1 ? clear bit. first, reads the data of reg1 to generate a 32-bit address. then clears the bit, specified by the data of lower 3 bits of reg2 of the byte data referenced by the generated address. cmov cccc, reg1, reg2, reg3 xi ? ? ? ? ? conditional move. reg3 is set to reg1 if a condition specified by condition code ?cccc? is satisfied; otherwise, set to the data of reg2. cmov cccc, imm5, reg2, reg3 xii ? ? ? ? ? conditional move. reg3 is set to the data of 5- immediate, sign-extended to word length, if a condition specified by condition code ?cccc? is satisfied; otherwise, set to the data of reg2. cmp reg1, reg2 i 0/1 0/1 0/1 0/1 ? compare. compares the word data of reg2 with the word data of reg1, and indicates the result by using the psw flags. to compare, the contents of reg1 are subtracted from the word data of reg2. cmp imm5, reg2 ii 0/1 0/1 0/1 0/1 ? compare. compares the word data of reg2 with the 5-bit immediate data, sign-extended to word length, and indicates the result by using the psw flags. to compare, the contents of the sign-extended immediate data are subtracted from the word data of reg2. ctret (none) x 0/1 0/1 0/1 0/1 0/1 restore from callt. restores the restore pc and psw from the appropriate system register and restores from a routine called by callt. dbret (none) x 0/1 0/1 0/1 0/1 0/1 return from debug trap. restores the restore pc and psw from the appropriate system register and restores from a debug monitor routine. dbtrap (none) i ? ? ? ? ? debug trap. saves the restore pc and psw to the appropriate system register and transfers control by setting the pc to handler address (00000060h). di (none) x ? ? ? ? ? disables interrupt. sets the id flag of the psw to 1 to disable the acknowledgement of maskable interrupts from acceptance; interrupts are immediatel y disabled at the start of this instruction execution. dispose imm5, list12 xiii ? ? ? ? ? function dispose. adds the data of 5-bit immediate imm5, logically shifted left by 2 and zero-extended to word length, to sp. then pop (load data from the address specified by sp and adds 4 to sp) general-purpose registers listed in list12.
appendix b instruction list 171 user?s manual u15943ej3v0um table b-1. instruction function list (in alphabetical order) (3/11) flag mnemonic operand format cy ov s z sat instruction function dispose imm5, list12, [reg1] xiii ? ? ? ? ? function dispose. adds the data of 5-bit immediate imm5, logically shifted left by 2 and zero-extended to word length, to sp. then pop (load data from the address specified by sp and adds 4 to sp) general-purpose registers listed in list12, transfers control to the address specified by reg1. div reg1, reg2, reg3 xi ? 0/1 0/1 0/1 ? divide word. divides the word data of reg2 by the word data of reg1, and stores the quotient to reg2 and the remainder to reg3. divh reg1, reg2 i ? 0/1 0/1 0/1 ? divide halfword. divides the word data of reg2 by the lower halfword data of reg1, and stores the quotient to reg2. divh reg1, reg2, reg3 xi ? 0/1 0/1 0/1 ? divide halfword. divides word data of reg2 by lower halfword data of reg1, and stores the quotient to reg2 and the remainder to reg3. divhu reg1, reg2, reg3 xi ? 0/1 0/1 0/1 ? divide halfword unsigned. divides word data of reg2 by lower halfword data of reg1, and stores the quotient to reg2 and the remainder to reg3. divu reg1, reg2, reg3 xi ? 0/1 0/1 0/1 ? divide word unsigned. divides the word data of reg2 by the word data of reg1, and stores the quotient to reg2 and the remainder to reg3. ei (none) x ? ? ? ? ? enable interrupt. clears the id flag of the psw to 0 and enables the acknowledgement of maskable interrupts at the beginning of next instruction. halt (none) x ? ? ? ? ? halt. stops the operating clock of the cpu and places the cpu in the halt mode. hsw reg2, reg3 xii 0/1 0 0/1 0/1 ? halfword swap word. performs endian conversion. jarl disp22, reg2 v ? ? ? ? ? jump and register link. saves the current pc value plus 4 to general-purpose register reg2, adds a 22-bit displacement, sign-extended to word length, to the current pc value, and transfers control to the pc. bit 0 of the 22-bit displacement is masked to 0. jmp [reg1] i ? ? ? ? ? jump register. transfers control to the address specified by reg1. bit 0 of the address is masked to 0. jr disp22 v ? ? ? ? ? jump relative. adds a 22-bit displacement, sign-extended to word length, to the current pc value, and transfers control to the pc. bit 0 of the 22-bit displacement is masked to 0.
appendix b instruction list 172 user?s manual u15943ej3v0um table b-1. instruction function list (in alphabetical order) (4/11) flag mnemonic operand format cy ov s z sat instruction function ld.b disp16 [reg1], reg2 vii ? ? ? ? ? byte load. adds the data of reg1 to a 16-bit displacement, sign-extended to word length, to generate a 32-bit address. byte data is read from the generated address, sign-extended to word length, and then stored in reg2. ld.bu disp16 [reg1], reg2 vii ? ? ? ? ? unsigned byte load. adds the data of reg1 and the 16-bit displacement sign-extended to word length, and generates a 32-bit address. then reads the byte data from the generated address, zero-extends it to word length, and stores it in reg2. ld.h disp16 [reg1], reg2 vii ? ? ? ? ? halfword load. adds the data of reg1 to a 16- bit displacement, sign-extended to word length, to generate a 32-bit address. halfword data is read from this 32-bit address with bit 0 masked to 0, sign-extended to word length, and stored in reg2. ld.hu disp16 [reg1], reg2 vii ? ? ? ? ? unsigned halfword load. adds the data of reg1 and the 16-bit displacement sign- extended to word length to generate a 32-bit address. reads the halfword data from the address masking bit 0 of this 32-bit address to 0, zero-extends it to word length, and stores it in reg2. ld.w disp16 [reg1], reg2 vii ? ? ? ? ? word load. adds the data of reg1 to a 16-bit displacement, sign-extended to word length, to generate a 32-bit address. word data is read from this 32-bit address with bits 0 and 1 masked to 0, and stored in reg2. ldsr reg2, regid ix ? ? ? ? ? load to system register. set the word data of reg2 to a system register specified by regid. if regid is psw, the values of the corresponding bits of reg2 are set to the respective flags of the psw. mov reg1, reg2 i ? ? ? ? ? move. transfers the word data of reg1 to reg2. mov imm5, reg2 ii ? ? ? ? ? move. transfers the value of a 5-bit immediate data, sign-extended to word length, to reg2. mov imm32, reg1 vi ? ? ? ? ? move. transfers the 32-bit immediate data to reg1. movea imm16, reg1, reg2 vi ? ? ? ? ? move effective address. adds a 16-bit immediate data, sign-extended to word length, to the word data of reg1, and stores the result in reg2.
appendix b instruction list 173 user?s manual u15943ej3v0um table b-1. instruction function list (in alphabetical order) (5/11) flag mnemonic operand format cy ov s z sat instruction function movhi imm16, reg1, reg2 vi ? ? ? ? ? move high halfword. adds word data, in which the higher 16 bits are defined by the 16-bit immediate data while the lower 16 bits are set to 0, to the word data of reg1 and stores the result in reg2. mul reg1, reg2, reg3 xi ? ? ? ? ? multiply word. multiplies the word data of reg2 by the word data of reg1, and stores the result in reg2 and reg3 as double-word data. mul imm9, reg2, reg3 xii ? ? ? ? ? multiply word. multiplies the word data of reg2 by the 9-bit immediate data sign-extended to word length, and stores the result in reg2 and reg3. mulh reg1, reg2 i ? ? ? ? ? multiply halfword. multiplies the lower halfword data of reg2 by the lower halfword data of reg1, and stores the result in reg2 as word data. mulh imm5, reg2 ii ? ? ? ? ? multiply halfword. multiplies the lower halfword data of reg2 by a 5-bit immediate data, sign- extended to halfword length, and stores the result in reg2 as word data. mulhi imm16, reg1, reg2 vi ? ? ? ? ? multiply halfword immediate. multiplies the lower halfword data of reg1 by a 16-bit immediate data, and stores the result in reg2. mulu reg1, reg2, reg3 xi ? ? ? ? ? multiply word unsigned. multiplies the word data of reg2 by the word data of reg1, and stores the result in reg2 and reg3 as double- word data. reg1 is not affected. mulu imm9, reg2, reg3 xii ? ? ? ? ? multiply word unsigned. multiplies the word data of reg2 by the 9-bit immediate data sign- extended to word length, and store the result in reg2 and reg3. nop (none) i ? ? ? ? ? no operation. not reg1, reg2 i ? 0 0/1 0/1 ? not. logically negates (takes 1?s complement of) the word data of reg1, and stores the result in reg2. not1 bit#3, disp16 [reg1] viii ? ? ? 0/1 ? not bit. first, adds the data of reg1 to a 16-bit displacement, sign-extended to word length, to generate a 32-bit address. the bit specified by the 3-bit bit number is inverted at the byte data location referenced by the generated address. not1 reg2, [reg1] ix ? ? ? 0/1 ? not bit. first, reads reg1 to generate a 32-bit address. the bit specified by the lower 3 bits of reg2 of the byte data of the generated address is inverted.
appendix b instruction list 174 user?s manual u15943ej3v0um table b-1. instruction function list (in alphabetical order) (6/11) flag mnemonic operand format cy ov s z sat instruction function or reg1, reg2 i ? 0 0/1 0/1 ? or. ors the word data of reg2 with the word data of reg1, and stores the result in reg2. ori imm16, reg1, reg2 vi ? 0 0/1 0/1 ? or immediate. ors the word data of reg1 with the 16-bit immediate data, zero-extended to word length, and stores the result in reg2. prepare list12, imm5 xiii ? ? ? ? ? function prepare. the general-purpose register displayed in list12 is saved (4 is subtracted from sp, and the data is stored in that address). next, the data is logically shifted 2 bits to the left, and the 5-bit immediate data zero-extended to word length is subtracted from sp. prepare list12, imm5, sp/imm xiii ? ? ? ? ? function prepare. the general-purpose register displayed in list12 is saved (4 is subtracted from sp, and the data is stored in that address). next, the data is logically shifted 2 bits to the left, and the 5-bit immediate data zero-extended to word length is subtracted from sp. then, the data specified by the third operand is loaded to ep. reti (none) x 0/1 0/1 0/1 0/1 0/1 return from trap or interrupt. reads the restore pc and psw from the appropriate system register, and restores from interrupt or exception processing routine. sar reg1, reg2 ix 0/1 0 0/1 0/1 ? shift arithmetic right. ar ithmetically shifts the word data of reg2 to the right by ?n? positions, where ?n? is specified by the lower 5 bits of reg1 (the msb prior to sh ift execution is copied and set as the new msb), and then writes the result to reg2. sar imm5, reg2 ii 0/1 0 0/1 0/1 ? shift arithmetic right. ar ithmetically shifts the word data of reg2 to the right by ?n? positions specified by the lower 5-bit immediate data, zero-extended to word length (the msb prior to shift execution is copied and set as the new msb), and then writes the result to reg2. sasf cccc, reg2 ix ? ? ? ? ? shift and set flag condition. reg2 is logically shifted left by 1, and its lsb is set to 1 in a condition specified by condition code ?cccc? is satisfied; otherwise, lsb is set to 0.
appendix b instruction list 175 user?s manual u15943ej3v0um table b-1. instruction function list (in alphabetical order) (7/11) flag mnemonic operand format cy ov s z sat instruction function satadd reg1, reg2 i 0/1 0/1 0/1 0/1 0/1 saturated add. adds the word data of reg1 to the word data of reg2, and stores the result in reg2. however, if the result exceeds the maximum positive value, the maximum positive value is stored in reg2; if the result exceeds the maximum negative value, the maximum negative value is stored in reg2. the sat flag is set to 1. satadd imm5, reg2 ii 0/1 0/1 0/1 0/1 0/1 saturated add. adds the 5-bit immediate data, sign-extended to word length, to the word data of reg2, and stores the result in reg2. however, if the result exceeds the maximum positive value, the maxi mum positive value is stored in reg2; if the result exceeds the maximum negative value, the maximum negative value is stored in reg2. the sat flag is set to 1. satsub reg1, reg2 i 0/1 0/1 0/1 0/1 0/1 saturated subtract. subtracts the word data of reg1 from the word data of reg2, and stores the result in reg2. however, if the result exceeds the maximum positive value, the maximum positive value is stored in reg2; if the result exceeds the maximum negative value, the maximum negative value is stored in reg2. the sat flag is set to 1. satsubi imm16, reg1, reg2 vi 0/1 0/1 0/1 0/1 0/1 saturated subtract immediate. subtracts a 16- bit immediate data, sign-extended to word length, from the word data of reg1, and stores the result in reg2. however, if the result exceeds the maximum positive value, the maximum positive value is stored in reg2; if the result exceeds the maximum negative value, the maximum negative value is stored in reg2. the sat flag is set to 1. satsubr reg1, reg2 i 0/1 0/1 0/1 0/1 0/1 saturated subtract reverse. subtracts the word data of reg2 from the word data of reg1, and stores the result in reg2. however, if the result exceeds the maximum positive value, the maximum positive value is stored in reg2; if the result exceeds the maximum negative value, the maximum negative value is stored in reg2. the sat flag is set to 1. set1 bit#3, disp16 [reg1] viii ? ? ? 0/1 ? set bit. first, adds a 16-bit displacement, sign- extended to word length, to the data of reg1 to generate a 32-bit address. the bits, specified by the 3-bit bit number, are set at the byte data location specified by the generated address.
appendix b instruction list 176 user?s manual u15943ej3v0um table b-1. instruction function list (in alphabetical order) (8/11) flag mnemonic operand format cy ov s z sat instruction function set1 reg2, [reg1] ix ? ? ? 0/1 ? set bit. first, reads the data of general- purpose register reg1 to generate a 32-bit address. the bit, specified by the data of lower 3 bits of reg2, is set at the byte data location referenced by the generated address. setf cccc, reg2 ix ? ? ? ? ? set flag condition. the reg2 is set to 1 if a condition specified by condition code "cccc" is satisfied; otherwise, a 0 is stored in reg2. shl reg1, reg2 ix 0/1 0 0/1 0/1 ? shift logical left. logically shifts the word data of reg2 to the left by ?n? positions (0 is shifted to the lsb side), where ?n? is specified by the lower 5 bits of reg1, and then writes the result to reg2. shl imm5, reg2 ii 0/1 0 0/1 0/1 ? shift logical left. logically shifts the word data of reg2 to the left by ?n? positions (0 is shifted to the lsb side), where ?n? is specified by a 5-bit immediate data, zero-extended to word length, and then writes the result to reg2. shr reg1, reg2 ix 0/1 0 0/1 0/1 ? shift logical right. logically shifts the word data of reg2 to the right by ?n? positions (0 is shifted to the msb side), where ?n? is specified by the lower 5 bits of reg1, and then writes the result to reg2. shr imm5, reg2 ii 0/1 0 0/1 0/1 ? shift logical right. logically shifts the word data of reg2 to the right by ?n? positions (0 is shifted to the msb side), where ?n? is specified by a 5-bit immediate data, zero-extended to word length, and then writes the result to reg2. sld.b disp7 [ep], reg2 iv ? ? ? ? ? byte load. adds the 7-bit displacement, zero- extended to word length, to the element pointer to generate a 32-bit address. byte data is read from the generated address, sign- extended to word length, and then stored in reg2. sld.bu disp4 [ep], reg2 iv ? ? ? ? ? unsigned byte load. adds the 4-bit displacement, zero-extended to word length, to the element pointer to generate a 32-bit address. byte data is read from the generated address, zero-extended to word length, and stored in reg2. sld.h disp8 [ep], reg2 iv ? ? ? ? ? halfword load. adds the 8-bit displacement, zero-extended to word length, to the element pointer to generate a 32-bit address. halfword data is read from the generated address, sign- extended to word length, and stored in reg2.
appendix b instruction list 177 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
appendix b instruction list 178 user?s manual u15943ej3v0um table b-1. instruction function list (in alphabetical order) (10/11) flag mnemonic operand format cy ov s z sat instruction function sub reg1, reg2 i 0/1 0/1 0/1 0/1 ? subtract. subtracts the word data of reg1 from the word data of reg2, and stores the result in reg2. subr reg1, reg2 i 0/1 0/1 0/1 0/1 ? subtract reverse. subtracts the word data of reg2 from the word data of reg1, and stores the result in reg2. switch reg1 i ? ? ? ? ? jump with table look up. adds the table entry address (address following switch instruction) and data of reg1 logically shifted to the left by 1 bit, and loads the halfword entry data specified by the table entry address. next, logically shifts to the left by 1 bit the loaded data, and after sign-extending it to word length, branches to the target address added to the table entry address (instruction following switch instruction). sxb reg1 i ? ? ? ? ? sign extend byte. sign-ex tends the lowermost byte of reg1 to word length. sxh reg1 i ? ? ? ? ? sign extend halfword. sign-extends lower halfword of reg1 to word length. trap vector x ? ? ? ? ? trap. saves the restore pc and psw; sets the exception code and the flags of the psw; jumps to the address of the trap handler corresponding to the trap vector specified by vector, and starts exception processing. tst reg1, reg2 i ? 0 0/1 0/1 ? test. ands the word data of reg2 with the word data of reg1. the result is not stored, and only the flags are changed. tst1 bit#3, disp16 [reg1] viii ? ? ? 0/1 ? test bit. adds the data of reg1 to a 16-bit displacement, sign-extended to word length, to generate a 32-bit address. performs the test on the bit, specified by the 3-bit bit number, at the byte data location referenced by the generated address. if the specified bit is 0, the z flag is set to 1; if the bit is 1, the z flag is cleared to 0. tst1 reg2, [reg1] ix ? ? ? 0/1 ? test bit. first, reads the data of reg1 to generate a 32-bit address. if the bits indicated by the lower 3 bits of reg2 of the byte data of the generated address are 0, the z flag is set to 1, and if they are 1, the z flag is cleared to 0. xor reg1, reg2 i ? 0 0/1 0/1 ? exclusive or. exclusiv ely ors the word data of reg2 with the word data of reg1, and stores the result in reg2.
appendix b instruction list 179 user?s manual u15943ej3v0um table b-1. instruction function list (in alphabetical order) (11/11) flag mnemonic operand format cy ov s z sat instruction function xori imm16, reg1, reg2 vi ? 0 0/1 0/1 ? exclusive or immediate. exclusively ors the word data of reg1 with a 16-bit immediate data, zero-extended to word length, and stores the result in reg2. zxb reg1 i ? ? ? ? ? zero extend byte. zero-extends to word length the lowest byte of reg1. zxh reg1 i ? ? ? ? ? zero extend halfword. zero-extends to word length the lower halfword of reg1.
appendix b instruction list 180 user?s manual u15943ej3v0um table b-2. instruction list (in format order) (1/3) opcode format 15 0 31 16 mnemonic operand 0000000000000000 ? nop ? rrrrr000000rrrrr ? mov reg1, reg2 rrrrr000001rrrrr ? not reg1, reg2 rrrrr000010rrrrr ? divh reg1, reg2 00000000010rrrrr ? switch reg1 00000000011rrrrr ? jmp [reg1] rrrrr000100rrrrr ? satsubr reg1, reg2 rrrrr000101rrrrr ? satsub reg1, reg2 rrrrr000110rrrrr ? satadd reg1, reg2 rrrrr000111rrrrr ? mulh reg1, reg2 00000000100rrrrr ? zxb reg1 00000000101rrrrr ? sxb reg1 00000000110rrrrr ? zxh reg1 00000000111rrrrr ? sxh reg1 rrrrr001000rrrrr ? or reg1, reg2 rrrrr001001rrrrr ? xor reg1, reg2 rrrrr001010rrrrr ? and reg1, reg2 rrrrr001011rrrrr ? tst reg1, reg2 rrrrr001100rrrrr ? subr reg1, reg2 rrrrr001101rrrrr ? sub reg1, reg2 rrrrr001110rrrrr ? add reg1, reg2 rrrrr001111rrrrr ? cmp reg1, reg2 i 1111100001000000 ? dbtrap ? rrrrr010000iiiii ? mov imm5, reg2 rrrrr010001iiiii ? satadd imm5, reg2 rrrrr010010iiiii ? add imm5, reg2 rrrrr010011iiiii ? cmp imm5, reg2 0000001000iiiiii ? callt imm6 rrrrr010100iiiii ? shr imm5, reg2 rrrrr010101iiiii ? sar imm5, reg2 rrrrr010110iiiii ? shl imm5, reg2 ii rrrrr010111iiiii ? mulh imm5, reg2 iii ddddd1011dddcccc ? bcond disp9
appendix b instruction list 181 user?s manual u15943ej3v0um table b-2. instruction list (in format order) (2/3) opcode format 15 0 31 16 mnemonic operand rrrrr0000110dddd ? sld.bu disp4 [ep], reg2 rrrrr0000111dddd ? sld.hu disp5 [ep], reg2 rrrrr0110ddddddd ? sld.b disp7 [ep], reg2 rrrrr0111ddddddd ? sst.b reg2, disp7 [ep] rrrrr1000ddddddd ? sld.h disp8 [ep], reg2 rrrrr1001ddddddd ? sst.h reg2, disp8 [ep] rrrrr1010dddddd0 ? sld.w disp8 [ep], reg2 iv rrrrr1010dddddd1 ? sst.w reg2, disp8 [ep] rrrrr11110dddddd ddddddddddddddd0 jarl disp22, reg2 v 0000011110dddddd ddddddddddddddd0 jr disp22 rrrrr110000rrrrr iiiiiiiiiiiiiiii addi imm16, reg1, reg2 rrrrr110001rrrrr iiiiiiiiiiiiiiii movea imm16, reg1, reg2 rrrrr110010rrrrr iiiiiiiiiiiiiiii movhi imm16, reg1, reg2 rrrrr110011rrrrr iiiiiiiiiiiiiiii satsubi imm16, reg1, reg2 00000110001rrrrr note mov imm32, reg1 rrrrr110100rrrrr iiiiiiiiiiiiiiii ori imm16, reg1, reg2 rrrrr110101rrrrr iiiiiiiiiiiiiiii xori imm16, reg1, reg2 rrrrr110110rrrrr iiiiiiiiiiiiiiii andi imm16, reg1, reg2 vi rrrrr110111rrrrr iiiiiiiiiiiiiiii mulhi imm16, reg1, reg2 rrrrr111000rrrrr dddddddddddddddd ld.b disp16 [reg1], reg2 rrrrr111001rrrrr ddddddddddddddd0 ld.h disp16 [reg1], reg2 rrrrr111001rrrrr ddddddddddddddd1 ld.w disp16 [reg1], reg2 rrrrr111010rrrrr dddddddddddddddd st.b reg2, disp16 [reg1] rrrrr111011rrrrr ddddddddddddddd0 st.h reg2, disp16 [reg1] rrrrr111011rrrrr ddddddddddddddd1 st.w reg2, disp16 [reg1] rrrrr11110brrrrr ddddddddddddddd1 ld.bu disp16 [reg1], reg2 vii rrrrr111111rrrrr ddddddddddddddd1 ld.hu disp16 [reg1], reg2 00bbb111110rrrrr dddddddddddddddd set1 bit#3, disp16 [reg1] 01bbb111110rrrrr dddddddddddddddd not1 bit#3, disp16 [reg1] 10bbb111110rrrrr dddddddddddddddd clr1 bit#3, disp16 [reg1] viii 11bbb111110rrrrr dddddddddddddddd tst1 bit#3, disp16 [reg1] note 32-bit immediate data. the higher 32 bits (bits 16 to 47) are as follows. 31 47 iiiiiiiiiiiiiiii iiiiiiiiiiiiiiii
appendix b instruction list 182 user?s manual u15943ej3v0um table b-2. instruction list (in format order) (3/3) opcode format 15 0 31 16 mnemonic operand rrrrr1111110cccc 0000000000000000 setf cccc, reg2 rrrrr111111rrrrr 0000000000100000 ldsr reg2, regid rrrrr111111rrrrr 0000000001000000 stsr regid, reg2 rrrrr111111rrrrr 0000000010000000 shr reg1, reg2 rrrrr111111rrrrr 0000000010100000 sar reg1, reg2 rrrrr111111rrrrr 0000000011000000 shl reg1, reg2 rrrrr111111rrrrr 0000000011100000 set1 reg2, [reg1] rrrrr111111rrrrr 0000000011100010 not1 reg2, [reg1] rrrrr111111rrrrr 0000000011100100 clr1 reg2, [reg1] rrrrr111111rrrrr 0000000011100110 tst1 reg2, [reg1] ix rrrrr1111110cccc 0000001000000000 sasf cccc, reg2 00000111111iiiii 0000000100000000 trap vector 0000011111100000 0000000100100000 halt ? 0000011111100000 0000000101000000 reti ? 0000011111100000 0000000101000100 ctret ? 0000011111100000 0000000101000110 dbret ? 0000011111100000 0000000101100000 di ? x 1000011111100000 0000000101100000 ei ? rrrrr111111rrrrr wwwww01000100000 mul reg1, reg2, reg3 rrrrr111111rrrrr wwwww01000100010 mulu reg1, reg2, reg3 rrrrr111111rrrrr wwwww01010000000 divh reg1, reg2, reg3 rrrrr111111rrrrr wwwww01010000010 divhu reg1, reg2, reg3 rrrrr111111rrrrr wwwww01011000000 div reg1, reg2, reg3 rrrrr111111rrrrr wwwww01011000010 divu reg1, reg2, reg3 xi rrrrr111111rrrrr wwwww011001cccc0 cmov cccc, reg1, reg2, reg3 rrrrr111111iiiii wwwww01001iiii00 mul imm9, reg2, reg3 rrrrr111111iiiii wwwww01001iiii10 mulu imm9, reg2, reg3 rrrrr111111iiiii wwwww011000cccc0 cmov cccc, imm5, reg2, reg3 rrrrr11111100000 wwwww01101000000 bsw reg2, reg3 rrrrr11111100000 wwwww01101000010 bsh reg2, reg3 xii rrrrr11111100000 wwwww01101000100 hsw reg2, reg3 0000011001iiiiil lllllllllllrrrrr dispose imm5, list12, [reg1] 0000011001iiiiil lllllllllll00000 dispose imm5, list12 0000011110iiiiil lllllllllll00001 prepare list12, imm5 xiii 0000011110iiiiil lllllllllllff011 prepare list12, imm5, sp/imm
183 user?s manual u15943ej3v0um appendix c instruction opcode map this chapter shows the opcode map fo r the instruction code shown below. (1) 16-bit format instruction 15 5 0 11 10 sub-opcode (see [b]) 4 opcode (see [a]) (2) 32-bit format instruction 15 5 0 11 10 31 16 20 21 4 14 13 12 26 27 19 18 17 sub-opcode (see [h]) opcode (see [a]) sub-opcode (see [e]) sub-opcode (see [d], [h]) sub-opcode (see [c]) sub-opcode (see [f], [g], [i]) remark operand convention symbol meaning r reg1: general-purpose register (used as source register) r reg2: general-purpose register (mainly used as destinat ion register. some are also used as source registers.) w reg3: general-purpose register (mainly used as remainder of di vision results or higher 32 bits of multiply results) bit#3 3-bit data for bit number specification imm -bit immediate data disp -bit displacement data cccc 4-bit data condition code specification
appendix c instruction opcode map 184 user?s manual u15943ej3v0um [a] opcode bit bit bit bit bits 6, 5 10 9 8 7 0,0 0,1 1,0 1,1 format 0 0 0 0 mov r, r nop note 1 not divh switch note 2 dbtrap undefined note 3 jmp note 4 sld.bu note 5 sld.hu note 6 i, iv 0 0 0 1 satsubr zxb note 4 satsub sxb note 4 satadd r, r zxh note 4 mulh sxh note 4 0 0 1 0 or xor and tst 0 0 1 1 subr sub add r, r cmp r, r i mov imm5, r satadd imm5, r 0 1 0 0 callt note 4 add imm5, r cmp imm5, r 0 1 0 1 shr imm5, r sar imm5, r shl imm5, r mulh imm5, r undefined note 4 ii 0 1 1 0 sld.b 0 1 1 1 sst.b 1 0 0 0 sld.h 1 0 0 1 sst.h 1 0 1 0 sld.w note 7 sst.w note 7 iv 1 0 1 1 bcond iii movhi satsubi 1 1 0 0 addi movea mov imm32, r note 4 dispose note 4 vi, xiii 1 1 0 1 ori xori andi mulhi undefined note 4 vi 1 1 1 0 ld.b ld.h note 8 ld.w note 8 st.b st.h note 8 st.w note 8 vii 1 1 1 1 jr jarl ld.bu note 10 prepare note 11 bit manipulation 1 note 9 ld.hu note 10 undefined note 11 expansion 1 note 12 v, vii, viii, xiii notes 1. if r (reg1) = r0 and r (reg2) = r0 (instruction without reg1 and reg2) 2. if r (reg1) r0 and r (reg2) = r0 (instr uction with reg1 and without reg2) 3. if r (reg1) = r0 and r (reg2) r0 (instruction without reg1 and with reg2) 4. if r (reg2) = r0 (instruction without reg2) 5. if bit 4 = 0 and r (reg2) r0 (instruction with reg2) 6. if bit 4 = 1 and r (reg2) r0 (instruction with reg2) 7. see [b] 8. see [c] 9. see [d] 10. if bit 16 = 1 and r (reg2) r0 (instruction with reg2) 11. if bit 16 = 1 and r (reg2) = r0 (instruction without reg2) 12. see [e]
appendix c instruction opcode map 185 user?s manual u15943ej3v0um [b] short format load/store in struction (displacement/sub-opcode) bit 0 bit 10 bit 9 bit 8 bit 7 0 1 0 1 1 0 sld.b 0 1 1 1 sst.b 1 0 0 0 sld.h 1 0 0 1 sst.h 1 0 1 0 sld.w sst.w [c] load/store instructi on (displacement/sub-opcode) bit 16 bit 6 bit 5 0 1 0 0 ld.b 0 1 ld.h ld.w 1 0 st.b 1 1 st.h st.w [d] bit manipulation instruction 1 (sub-opcode) bit 14 bit 15 0 1 0 set1 bit#3, disp16 [r] not1 bit#3, disp16 [r] 1 clr1 bit#3, disp16 [r] tst1 bit#3, disp16 [r]
appendix c instruction opcode map 186 user?s manual u15943ej3v0um [e] expansi on 1 (sub-opcode) bits 22, 21 bit 26 bit 25 bit 24 bit 23 0,0 0,1 1,0 1,1 format 0 0 0 0 setf ldsr stsr undefined 0 0 0 1 shr sar shl bit manipulation 2 note 1 ix 0 0 1 0 trap halt reti note 2 ctret note 2 dbret note 2 undefined ei note 3 di note 3 undefined x 0 0 1 1 undefined undefined ? 0 1 0 0 sasf mul r, r, w mulu r, r, w note 4 mul imm9, r, w mulu imm9, r, w note 4 ix, xi, xii 0 1 0 1 divh divhu note 4 div divu note 4 xi 0 1 1 0 cmov cccc, imm5, r, w cmov cccc, r, r, w bsw note 5 bsh note 5 hsw note 5 undefined xi, xii 0 1 1 1 1 x x x illegal instruction ? notes 1. see [f] 2. see [g] 3. see [h] 4. if bit 17 = 1 5. see [i] [f] bit manipulation instruction 2 (sub-opcode) bit 17 bit 18 0 1 0 set1 r, [r] not1 r, [r] 1 clr1 r, [r] tst1 r, [r] [g] return instruction (sub-opcode) bit 17 bit 18 0 1 0 reti undefined 1 ctret dbret
appendix c instruction opcode map 187 user?s manual u15943ej3v0um [h] psw operation instruction (sub-opcode) bits 13, 12, 11 bit 15 bit 14 0,0,0 0,0,1 0,1,0 0,1,1 1,0,0 1,0,1 1,1,0 1,1,1 0 0 di undefined 0 1 undefined 1 0 ei undefined 1 1 undefined [i] endian conversion instruction (sub-opcode) bit 17 bit 18 0 1 0 bsw bsh 1 hsw undefined
188 user?s manual u15943ej3v0um appendix d differences in architecture of v850 cpu and v850e1 cpu (1/3) item v850es cpu v850e1 cpu v850 cpu bsh reg2, reg3 bsw reg2, reg3 callt imm6 clr1 reg2, [reg1] cmov cccc, imm5, reg2, reg3 cmov cccc, reg1, reg2, reg3 ctret provided dbret dbtrap provided provided note dispose imm5, list12 dispose imm5, list12 [reg1] div reg1, reg2, reg3 divh reg1, reg2, reg3 divhu reg1, reg2, reg3 divu reg1, reg2, reg3 hsw reg2, reg3 ld.bu disp16 [reg1], reg2 ld.hu disp16 [reg1], reg2 mov imm32, reg1 mul imm9, reg2, reg3 mul reg1, reg2, reg3 mulu reg1, reg2, reg3 mulu imm9, reg2, reg3 not1 reg2, [reg1] prepare list12, imm5 prepare list12, imm5, sp/imm sasf cccc, reg2 set1 reg2, [reg1] sld.bu disp4 [ep], reg2 sld.hu disp5 [ep], reg2 switch reg1 sxb reg1 sxh reg1 tst1 reg2, [reg1] zxb reg1 instructions (including operand) zxh reg1 provided not provided note not supported in the nb85e and nb85et
appendix d differences in architecture of v850 cpu and v850e1 cpu 189
appendix d differences in architecture of v850 cpu and v850e1 cpu 190 user?s manual u15943ej3v0um (3/3) item v850es cpu v850e1 cpu v850 cpu ? word data multiply instruction note 1 note 1 no instructions pipeline ? arithmetic operation instruction other than word data multiply instruction ? branch instruction ? bit manipulation instruction ? special instruction (trap, reti) note 2 note 2 notes 1. the pipeline flow differs between the v850es cpu core and the v850e1 cpu core. for details, refer to chapter 8 pipeline and v850e1 architecture user?s manual (u14559e) . 2. the pipeline flow differs between the v850es and v850e1 cpu cores and the v850 cpu core. for details, refer to chapter 8 pipeline , v850e1 architecture user?s manual (u14559e) , and v850 series architecture user?s manual (u10243e ).
191 user?s manual u15943ej3v0um appendix e instructions added for v 850es cpu compared with v850 cpu compared with the instructi on codes of the v850 cpu, the instruction codes of the v850es cpu are upwardly compatible at the object code level. in the case of the v850es cpu, inst ructions that even if executed have no meaning in the case of the v850 cpu (mainly instructions performing write to the r0 register) are extended as additional instructions. the following table shows the v850 cp u instructions corresponding to the instruction codes added in the v850es cpu. see the table when swit ching from products that in corporate the v850 cpu to pr oducts that incorporate the v850es cpu. since the v850es cpu is compatible with all the instruction codes of the v850e1 cpu, t hese products are replaced easily. table e-1. instructions added to v850es cpu and v 850 cpu instructions with same instruction code (1/2) instructions added in v850es cpu v850 cpu instructions with same instruction code as v850es cpu callt imm6 mov imm5, r0 or satadd imm5, r0 dispose imm5, list12 movhi imm16, reg1, r0 or satsubi imm16, reg1, r0 dispose imm5, list12 [reg1] movhi imm16, r eg1, r0 or satsubi imm16, reg1, r0 mov imm32, reg1 movea imm16, reg1, r0 switch reg1 divh reg1, r0 sxb reg1 satsub reg1, r0 sxh reg1 mulh reg1, r0 zxb reg1 satsubr reg1, r0 zxh reg1 satadd reg1, r0 (rfu) mulh imm5, r0 (rfu) mulhi imm16, reg1, r0 bsh reg2, reg3 bsw reg2, reg3 cmov cccc, imm5, reg2, reg3 cmov cccc, reg1, reg2, reg3 ctret div reg1, reg2, reg3 divh reg1, reg2, reg3 divhu reg1, reg2, reg3 divu reg1, reg2, reg3 hsw reg2, reg3 mul imm9, reg2, reg3 mul reg1, reg2, reg3 mulu reg1, reg2, reg3 mulu imm9, reg2, reg3 sasf cccc, reg2 illegal instruction
appendix e instructions added for v850es cpu compared with v850 cpu 192 user?s manual u15943ej3v0um table e-1. instructions added to v850es cpu and v 850 cpu instructions with same instruction code (2/2) instructions added in v850es cpu v850 cpu instructions with same instruction code as v850es cpu clr1 reg2, [reg1] dbret dbtrap ld.bu disp16 [reg1], reg2 ld.hu disp16 [reg1], reg2 not1 reg2, [reg1] prepare list12, imm5 prepare list12, imm5, sp/imm set1 reg2, [reg1] sld.bu disp4 [ep], reg2 sld.hu disp5 [ep], reg2 tst1 reg2, [reg1] undefined
193 user?s manual u15943ej3v0um appendix f revision history f.1 major revisions in this edition page description p. 15 modification of figure 2-1 registers p. 16 modification of description in 2.1 (1) general-purpose registers (r0 to r31) p. 18 modification of table 2-2 system register numbers p. 24 addition of 2.2.8 debug interface register (dir) p. 82 modification of caution in 5.3 instruction set mul p. 85 modification of caution in 5.3 instruction set mulu p. 106 addition of caution (2) to 5.3 instruction set sld.b p. 107 addition of caution (2) to 5.3 instruction set sld.bu p. 108 addition of caution (2) to 5.3 instruction set sld.h p. 109 addition of caution (2) to 5.3 instruction set sld.hu p. 110 addition of caution (2) to 5.3 instruction set sld.w p. 132 addition of note 4 to table 5-6 list of number of instruction execution cock cycles p. 140 addition of description to 6.2.3 debug trap p. 141 deletion of note from 6.3.1 restoring from interrupt and software exception p. 142 addition of (3) to 6.3.2 restoring from exception trap and debug trap p. 143 addition of description to table 7-1 register status after reset p. 147 addition of remark to 8.1.2 2-clock branch p. 168 addition of appendix a notes p. 189 modification of appendix d differences in architecture of v850 cpu and v850e1 cpu p. 193 modification of appendix f revision history f.2 history of revisions up to this edition a history of the revisions up to this edition is shown bel ow. ?applied to:? indicates the chapters to which the revision was applied. edition major revisions from previous edition applied to: modification of description of v850es cpu core in figure 1-1 v850 series cpu development chapter 1 general addition of description of caution in 5.3 instruction set mul addition of description of caution in 5.3 instruction set mulu chapter 5 instruction modification of description of pipeline in appendix c differences in architecture of v850 cpu and v850e1 cpu appendix c differences in architecture of v850 cpu and v850e1 cpu 2nd addition of appendix f revision history appendix f revision history

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